US4565932A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High voltage circuit for use in programming memory circuits (EEPROMs)
Assignee: Motorola Solutions Inc
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Filing: 1983-12-29
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Granted: 1986-01-21
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Expires: 2003-12-29
Abstract
Abstract A high voltage circuit provides a high voltage signal output in response to receiving a logic signal. The high voltage circuit includes a regenerative circuit which is coupled to a high voltage terminal and a 5 volt power supply terminal. An inverting push-pull buffer responsive to the logic signal provides a signal which is regenerated to the high voltage by the regenerative circuit when the logic signal is in a first state and maintains the signal at ground potential when the logic signal is in a second logic state.
Inventors
- 👤 Clinton C. K. Kuo
- 👤 Sam Dehganpour
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 01:34
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/01; H03K19/017; H03K19/01707; H03K19/01721; H02; H02M; H02M3/00; H02M3/02; H02M3/04; H02M3/10; H02M3/145; H02M3/155; H03F; H03F3/00; H03F3/34; H03F3/343; H03F3/345; H03K19/0175; H03K19/0185
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
89 words
A high voltage circuit, comprising: a first transistor having a control electrode for receiving an input signal, a first current electrode coupled to a first power supply terminal, and a second current electrode; a load coupled between an output node and the second current electrode of the first transistor; and a second transistor having a control electrode coupled to the output node, a first current electrode coupled to a high voltage power supply terminal, and a second current electrode coupled to the second current electrode of the first transistor.
Claim 2
Dependent Claim
89 words
A high voltage circuit, comprising: a first transistor having a control electrode for receiving an input signal, a first current electrode coupled to a first power supply terminal, and a second current electrode; a load coupled between an output node and the second current electrode of the first transistor; and a second transistor having a control electrode coupled to the output node, a first current electrode coupled to a high voltage power supply terminal, and a second current electrode coupled to the second current electrode of the first transistor.
Claim 3
Dependent Claim
29 words
The high voltage circuit of claim 1 further comprising an inverting push-pull buffer having an input for receiving the input signal, and an output coupled to the output node.
Claim 4
Dependent Claim
66 words
The high voltage circuit of claim 2 further comprising a third transistor, interposed between the output node and the load device and the control electrode of the second transistor, having a first current electrode coupled to the output node, a second current electrode coupled to the control electrode of the second transistor and the load device, and a control electrode coupled to the high voltage terminal.
Claim 5
Dependent Claim
95 words
The high voltage circuit of claim 3 wherein the inverting push-pull buffer comprises: an inverter having an input for receiving the input signal, and an output; a fourth transistor having a control electrode coupled to the output of the inverter, a first current electrode coupled to the first power supply terminal, and a second current electrode coupled to the output node; and a fifth transistor having a control electrode for receiving the input signal, a first current electrode coupled to the output node, and a second current electrode coupled to a second power supply terminal.
Claim 6
Dependent Claim
64 words
The high voltage circuit of claim 4 further comprising a sixth transistor, interposed between the second current electrode of the fifth transistor and the second power supply terminal, having a first current electrode coupled to the second current electrode of the fifth transistor, a second current electrode coupled to the second power supply terminal, and a control electrode for receiving a second input signal.
Claim 7
Dependent Claim
46 words
The high voltage circuit of claim 5 wherein the load comprises a seventh transistor having first current electrode coupled to the second current electrode of the first transistor, and a second current electrode and a control electrode coupled to the control electrode of the second transistor.
Claim 8
Dependent Claim
15 words
The high voltage circuit of claim 1 wherein the second transistor is a depletion transistor.
Claim 9
Dependent Claim
26 words
The circuit of claim 7 further comprising an inverting buffer having an input for receiving the input signal, and an output coupled to the output node.
Claim 10
Dependent Claim
45 words
The circuit of claim 8 wherein the load comprises a third transistor having a first current electrode coupled to the second current electrode of the first transistor, and a second current electrode and a control electrode coupled to the control electrode of the second transistor.
Claim 11
Dependent Claim
20 words
The circuit of claim 9 further comprising means for disabling the inverting buffer in response to a second input signal.
Claim 12
Dependent Claim
80 words
The high voltage circuit of claim 10 further comprising a fourth transistor, interposed between the output node and the second and control electrodes of the third transistor and the control electrode of the second transistor, having a first current electrode coupled to the output node, a second current electrode coupled to the second and control electrodes of the third transistor and the control electrode of the second transistor, and a control electrode coupled to the high voltage power supply terminal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-01-20 | 1989-07-22 | 1990-01-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-01-20 | 1993-07-22 | 1994-01-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-01-20 | 1997-07-22 | 1998-01-21 | $7700.00 | Window Closed / Lapsed |