Method of multiplexing liquid crystal displays

Claim 2

A circuit for alternating a data signal from between a first and second voltage level to between a second and third voltage level at an output comprising: a data input, an alternating signal input, a first switch means for providing said first voltage level at said output, a second switch means for providing said second voltage level at said output, a third switch means for providing said third voltage level at said output, an inverter means between said data input and said second switch means, a NOR gate means for receiving said data and alternating signal inputs and producing an output coupled to said third switch means, and a NAND gate means for receiving said alternating signal input and the output of said inverter and producing an output cooupled to said first switch means.

Claim 3

The circuit of claim 1 wherein said first and second switch means are P channel field effect transistors and said third switch means is an N channel field effect transistor.

Claim 4

In a liquid display having a digit drive signal varying between a first and second voltage level and a segment drive signal varying between said second voltage level and a third voltage level and polarity reversal means for periodically producing a reversal of current flow through the liquid crystal display, the improvement comprising: a pair of polarity reversal logic means, one for producing a digit drive signal which periodically varies between said first and second voltage levels and said second and third voltage levels, and one for producing a segment drive signal which periodically varies between said second and third voltage levels and said first and second voltage levels in coincidence with the variation of said digit drive signal, each of said polarity reversal logic means including a first input for receiving an alternating periodic signal, second, third and fourth inputs for receiving said first, second and third voltage levels respectively and a fifth input for receiving a select signal, first switch means for connecting said first voltage level input to the output of said polarity reversal logic means, a second switch means for connecting said second voltage level input to said polarity reversal logic means output, third switch means for connecting said third voltage level input to said polarity reversal logic means output, an inverter means connected between said select signal input and said second switch means, a NOR gate having first and second inputs connected, respectively, to said select signal input and said alternating signal input and an output connected to said third switch means, a NAND gate having first and second inputs connected, respectively, to said alternating signal input and the output of said inverter means and having an output connected to said first switch means.

Claim 5

In a liquid display having a digit drive signal varying between a first and second voltage level and a segment drive signal varying between said second voltage level and a third voltage level and polarity reversal means for periodically producing a reversal of current flow through the liquid crystal display, the improvement comprising: a pair of polarity reversal logic means, one for producing a digit drive signal which periodically varies between said first and second voltage levels and said second and third voltage levels, and one for producing a segment drive signal which periodically varies between said second and third voltage levels and said first and second voltage levels in coincidence with the variation of said digit drive signal, each of said polarity reversal logic means including a first input for receiving an alternating periodic signal, second, third and fourth inputs for receiving said first, second and third voltage levels respectively and a fifth input for receiving a select signal, first switch means for connecting said first voltage level input to the output of said polarity reversal logic means, a second switch means for connecting said second voltage level input to said polarity reversal logic means output, third switch means for connecting said third voltage level input to said polarity reversal logic means output, an inverter means connected between said select signal input and said second switch means, a NOR gate having first and second inputs connected, respectively, to said select signal input and said alternating signal input and an output connected to said third switch means, a NAND gate having first and second inputs connected, respectively, to said alternating signal input and the output of said inverter means and having an output connected to said first switch means.

Claim 6

A circuit for causing a data signal to periodically reverse polarity comprising: a data input, an alternating signal input, a first P channel field effect transistor means for providing a first voltage level at said output, a second P channel field effect transistor means for providing a second voltage level at said output, a third N channel field effect transistor means for providing third voltage level at said output, the difference between said second and third voltage levels being equal in magnitude and difference between said first and second voltages but opposite in polarity, an inverter means connected between said data input and said second transistor means, a NOR gate the inputs of which are connected to receive said data and alternating signal inputs, the output of said NOR gate being connected to said third transistor means, and a NAND gate the inputs of which are connected to receive said alternating signal input and the output of said inverter, the output of said NAND gate being connected to said first transistor means.

Claim 7

A circuit for causing a data signal to periodically reverse polarity comprising: a data input, an alternating signal input, a first P channel field effect transistor means for providing a first voltage level at said output, a second P channel field effect transistor means for providing a second voltage level at said output, a third N channel field effect transistor means for providing third voltage level at said output, the difference between said second and third voltage levels being equal in magnitude and difference between said first and second voltages but opposite in polarity, an inverter means connected between said data input and said second transistor means, a NOR gate the inputs of which are connected to receive said data and alternating signal inputs, the output of said NOR gate being connected to said third transistor means, and a NAND gate the inputs of which are connected to receive said alternating signal input and the output of said inverter, the output of said NAND gate being connected to said first transistor means.