Programmable read only memory operable with reduced programming power consumption

Claim 2

A semiconductor memory comprising a plurality of memory cells each including a first field effect transistor of one conductivity type having a floating gate, a reference terminal supplied with a reference voltage, a node, means responsive to address information for selecting at least one of said memory cells to connect said at least one memory cell between said reference terminal and said node, a programming terminal supplied with a programming voltage, through a second field effect transistor of an opposite conductivity type connected between said programming terminal and said node, and means for supplying a gate of said second field effect transistor in a programming operation with a writing voltage having an intermediate level between said programming voltage and said reference voltage, whereby said second field effect transistor contributes to make a current flowing through the selected memory cell substantially constant before and after said selected memory cell is programmed.

Claim 3

The memory as claimed in claim 1, said writing voltage being approximately equal to a voltage supplied to the selected memory cell in a read-out operation.

Claim 4

A semiconductor memory comprising at least one first transistor of one conductivity type having a floating gate, said first transistor constituting a memory cell, a first terminal supplied with a reference voltage, a circuit node, means for connecting said first transistor between said first terminal and said circuit node, a second terminal supplied with a first voltage in a programming operation, a second transistor of an opposite conductivity type connected between said second terminal and said circuit node, a third terminal supplied with a second voltage in said programming operation, said second voltage being an intermediate voltage between said reference voltage and said first voltage, a third transistor of said opposite conductivity type connected between said second terminal and a gate of said second transistor, a fourth transistor of said one conductivity type connected between said third terminal and the gate of said second transistor, gates of said third and fourth transistors being connected in common, and means for supplying gates of said third and fourth transistors in said programming operation with such a control voltage that turns said fourth transistors ON and said third transistor OFF to apply said second voltage to the gate of said second transistor.

Claim 5

A semiconductor memory comprising at least one first transistor of one conductivity type having a floating gate, said first transistor constituting a memory cell, a first terminal supplied with a reference voltage, a circuit node, means for connecting said first transistor between said first terminal and said circuit node, a second terminal supplied with a first voltage in a programming operation, a second transistor of an opposite conductivity type connected between said second terminal and said circuit node, a third terminal supplied with a second voltage in said programming operation, said second voltage being an intermediate voltage between said reference voltage and said first voltage, a third transistor of said opposite conductivity type connected between said second terminal and a gate of said second transistor, a fourth transistor of said one conductivity type connected between said third terminal and the gate of said second transistor, gates of said third and fourth transistors being connected in common, and means for supplying gates of said third and fourth transistors in said programming operation with such a control voltage that turns said fourth transistors ON and said third transistor OFF to apply said second voltage to the gate of said second transistor.

Claim 6

The memory as claimed in claim 3, wherein said control voltage has an amplitude between said reference voltage and said first voltage and said fourth transistor is turned ON when said control voltage takes said first voltage, said third transistor being turned ON when said control voltage takes said reference voltage.

Claim 7

The memory as claimed in claim 3, wherein said second terminal is supplied with said second voltage in a read-out operation and said second transistor is held in an off-state.

Claim 8

A semiconductor memory comprising a plurality of word lines, a plurality of digit lines, a plurality of N-channel type memory transistors, each of said memory transistors having a floating gate, a control gate connected to one of said word lines and a source-drain current path connected between one of said digit lines and a reference potential point, a circuit node, a plurality of gate transistors, each of said gate transistors being connected between said circuit node and an associated one of said digit lines, a first decoder energizing one of said word lines in response to a first set of address signals, a second decoder turning ON one of said gate transistors in response to a second set of address signals, a first terminal supplied with a programming voltage in a programming operation, a second terminal supplied with an intermediate voltage between said programming voltage and a reference potential at said reference potential point, a switching transistor of a P-channel type having a source-drain current path connected between said first terminal and said circuit node, a third terminal receiving a programming control signal, means for producing a writing signal in response to said programming control signal, said writing signal taking either one of a first level substantially equal to said reference potential and a second level substantially equal to said programming voltage, a level conversion circuit converting said first and second levels of said writing signal into third and fourth levels, said third level being substantially equal to said intermediate voltage and said fourth level being substantially equal to said programming voltage, and means for applying the output of said level conversion circuit to a gate of said switching transistor.

Claim 9

A semiconductor memory comprising a plurality of word lines, a plurality of digit lines, a plurality of N-channel type memory transistors, each of said memory transistors having a floating gate, a control gate connected to one of said word lines and a source-drain current path connected between one of said digit lines and a reference potential point, a circuit node, a plurality of gate transistors, each of said gate transistors being connected between said circuit node and an associated one of said digit lines, a first decoder energizing one of said word lines in response to a first set of address signals, a second decoder turning ON one of said gate transistors in response to a second set of address signals, a first terminal supplied with a programming voltage in a programming operation, a second terminal supplied with an intermediate voltage between said programming voltage and a reference potential at said reference potential point, a switching transistor of a P-channel type having a source-drain current path connected between said first terminal and said circuit node, a third terminal receiving a programming control signal, means for producing a writing signal in response to said programming control signal, said writing signal taking either one of a first level substantially equal to said reference potential and a second level substantially equal to said programming voltage, a level conversion circuit converting said first and second levels of said writing signal into third and fourth levels, said third level being substantially equal to said intermediate voltage and said fourth level being substantially equal to said programming voltage, and means for applying the output of said level conversion circuit to a gate of said switching transistor.

Claim 10

The memory as claimed in claim 6, wherein said first terminal is supplied with said intermediate voltage in a read-out operation and said switching transistor is maintained OFF in said read-out operation.