EEPROM memory cell and driving circuitry

Claim 1

An electrically erasable programmable semiconductor memory cell, comprising: a floating gate on a face of a semiconductor body; a channel beneath said floating gate; a dielectric layer disposed between said channel and said floating gate; heavily- and lightly-doped, spaced-apart source and drain regions of a first conductivity type in said face on either side of the channel; a single control gate spaced from and overlying said floating gate, said control gate aligned with said floating gate on both sides of said channel; a sidewall spacer adhered to one side of said floating gate and said overlying control gate; wherein one of the lightly-doped regions of said heavily- and lightly-doped source and drain regions forms a reach through region beneath and overlapped by an edge portion of said floating gate opposite said sidewall spacer, said reach-through region being separated from said floating gate by said dielectric layer and providing a source of electrons over a surface uniformly spaced from said floating gate from which tunneling to and from the floating gate can take place; wherein the thickness of said dielectric layer between said floating gate and said channel is approximately the same as the thickness of said dielectric layer between said floating gate and said overlapped portion of said reach-through region; wherein tunneling of electrons between said reach-through region and said floating gate takes place upon the electric field between the channel and floating gate exceeding a threshold value.