Process for the fabrication of a nonvolatile memory cell with very small thin oxide area and cell

Claim 1

Process for the fabrication of a nonvolatile memory cell with very small thin oxide area characterized in that it comprises: (a) preparation of a monocrystalline silicon substrate of a first conductivity type covered with a layer of oxide and a layer of nitride; (b) etching of said oxide layer and said nitride layer in a predetermined area and doping of the underlying silicon substrate with an opposite conductivity type modifier in said area; (c) growth of thick field oxide on said doped area of the silicon substrate; (d) etching of a side portion of predetermined dimensions of said thick field oxide with underetching under the nitride layer until an edge of the underlying doped area of the silicon substrate is exposed; (e) etching of the nitride layer; (f) growth of thin oxide over said uncovered edge of the silicon-substrate to form a floating gate oxide; (g) final deposit of a first floating gate and a second control gate layer of polycrystalline silicon on said thin oxide with interposition between said first floating gate and said second control gate of an oxide layer.