US4649521A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Programmable read-only memory (PROM) device having reduced programming voltage capability
Assignee: Fujitsu Ltd
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Filing: 1984-11-26
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Granted: 1987-03-10
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Expires: 2004-11-26
Abstract
Abstract A programmable read-only memory device comprising a memory cell transistor which has a floating gate and a control gate formed above the floating gate. The programmable read-only memory device further comprises a means for delaying the application timing of a high voltage to the control gate from that of a high voltage to the drain of the memory cell transistor when a data programming operation is performed by applying the high voltage to the control gate and the drain of the memory cell transistor, thereby ensuring reliable a data write operation even at a low programming voltage.
Inventors
- 👤 Manabu Tsuchida
- 👤 Masanobu Yoshida
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 04:12
CPC Classifications
G; G11; G11C; G11C17/00; G11C16/00; G11C16/02; G11C16/06; G11C16/32
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
270 words
A programmable read-only memory device comprising: a plurality of memory cell transistors arrayed in columns and rows and each having a source, a drain, a floating gate and a control gate formed above said floating gate; a means for generating a column selection signal which applies a high programming voltage to the drain of a memory cell transistor of a selected column under control of a program signal, said means being connected to a source of a high programming voltage, the drain of said memory cell transistor and said program signal; a means for generating a row selection signal which applies a high programming voltage to the control gate of a memory cell transistor of a selected row under control of a delayed-program signal; and a delay means for receiving said program signal, and for generating a delayed-program signal supplied to said means for generating a row selection signal, for delaying the application timing of said high programming voltage from said means for generating a row selection signal to the control gate of the memory cell transistor of the selected row with respect to the application timing of the high programming voltage from said means for generating a column selection signal to the drain of the memory cell transistor of the selected column, whereby a programming operation is performed for a memory cell transistor of a selected column and row by applying the high programming voltage to the control gate of the memory cell transistor at an application timing delayed with respect to the application timing of the high programming voltage applied to the drain of the memory cell transistor.
Claim 2
Dependent Claim
270 words
A programmable read-only memory device comprising: a plurality of memory cell transistors arrayed in columns and rows and each having a source, a drain, a floating gate and a control gate formed above said floating gate; a means for generating a column selection signal which applies a high programming voltage to the drain of a memory cell transistor of a selected column under control of a program signal, said means being connected to a source of a high programming voltage, the drain of said memory cell transistor and said program signal; a means for generating a row selection signal which applies a high programming voltage to the control gate of a memory cell transistor of a selected row under control of a delayed-program signal; and a delay means for receiving said program signal, and for generating a delayed-program signal supplied to said means for generating a row selection signal, for delaying the application timing of said high programming voltage from said means for generating a row selection signal to the control gate of the memory cell transistor of the selected row with respect to the application timing of the high programming voltage from said means for generating a column selection signal to the drain of the memory cell transistor of the selected column, whereby a programming operation is performed for a memory cell transistor of a selected column and row by applying the high programming voltage to the control gate of the memory cell transistor at an application timing delayed with respect to the application timing of the high programming voltage applied to the drain of the memory cell transistor.
Claim 3
Dependent Claim
38 words
A programmable read-only memory device according to claim 1, wherein said delay means comprises one or more inverters connected in cascade, and one or more capacitors each being connected respectively to an output of one of said inverters.
Claim 4
Dependent Claim
139 words
A programmable read-only memory device according to claim 1, wherein said means for generating a row selection signal comprises: a gate circuit for decoding input row addresses, a high breakdown voltage depletion type transistor having a source connected to an output terminal of said gate circuit and having a gate which receives a power supply voltage, and a high breakdown voltage zero threshold voltage type transistor having a gate which receives said delayed program signal and a high breakdown voltage low threshold voltage depletion type transistor whose gate and source are interconnected, said high breakdown voltage zero threshold voltage type transistor and said high breakdown voltage low threshold voltage depletion type transistor being connected in series and said series-connected transistors being inserted between a high voltage power supply and a drain of said high breakdown voltage depletion type transistor.
Claim 5
Dependent Claim
138 words
A programmable read-only memory device according to claim 1, wherein said means for generating a column selecting signal comprises: a gate circuit for decoding input column addresses, a high breakdown voltage depletion type transistor having a source connected to an output terminal of said gate circuit and having a gate which receives a power supply voltage, and a high breakdown voltage zero threshold voltage type transistor having a gate which receives said program signal and a high breakdown voltage low threshold voltage depletion type transistor whose gate and source are interconnected, said high breakdown voltage zero threshold voltage type transistor and said high breakdown voltage low threshold voltage depletion type transistor being connected in series and said series-connected transistors being inserted between a high voltage power supply and a drain of said high breakdown voltage depletion type transistor.
Claim 6
Dependent Claim
220 words
A programmable read-only memory device comprising: a plurality of memory cell transistors arrayed in columns and rows and each having a source, a drain, a floating gate, and a control gate formed above said floating gate; a means for generating a column selection signal which applies a high programming voltage to the drain of a memory cell transistor of a selected column; a first power switch circuit for generating internal power supply voltages supplied to said means for generating a column selection signal under the control of a program signal; a means for generating a row selection signal which applies a high programming voltage to the control gate of a memory cell transistor of a selected row; a second power switch circuit for generating internal power supply voltage supplied to said means for generating a row selection signal under the control of a delayed-program signal; and a delay means for generating said delayed-program signal for delaying the application timing of a high programming voltage to the control gate of a selected one of said memory cell transistors from the application timing of a high programming voltage to the drain of said selected memory cell transistor when a data programming operation is performed by applying said high programming voltages to the control gate and drain of said selected memory cell transistor.
Claim 7
Dependent Claim
220 words
A programmable read-only memory device comprising: a plurality of memory cell transistors arrayed in columns and rows and each having a source, a drain, a floating gate, and a control gate formed above said floating gate; a means for generating a column selection signal which applies a high programming voltage to the drain of a memory cell transistor of a selected column; a first power switch circuit for generating internal power supply voltages supplied to said means for generating a column selection signal under the control of a program signal; a means for generating a row selection signal which applies a high programming voltage to the control gate of a memory cell transistor of a selected row; a second power switch circuit for generating internal power supply voltage supplied to said means for generating a row selection signal under the control of a delayed-program signal; and a delay means for generating said delayed-program signal for delaying the application timing of a high programming voltage to the control gate of a selected one of said memory cell transistors from the application timing of a high programming voltage to the drain of said selected memory cell transistor when a data programming operation is performed by applying said high programming voltages to the control gate and drain of said selected memory cell transistor.
Claim 8
Dependent Claim
97 words
A programmable read-only memory device according to claim 5, wherein said first power switch circuit comprises first and second high breakdown voltage transistors which are alternately turned on by said program signal, said first high breakdown voltage transistor supplying a high internal power supply voltage to said means for generating a column selection signal when said first high breakdown voltage transistor is turned on, and said second high breakdown voltage transistor supplying a low internal power supply voltage to said means for generating a column selection signal when said second high breakdown voltage transistor is turned on.
Claim 9
Dependent Claim
98 words
A programmable read-only memory device according to claim 5, wherein said second power switch circuit comprises first and second high breakdown voltage transistors which are alternately turned on by said delayed program signal, said first high breakdown voltage transistor supplying a high internal power supply voltage to said means for generating a row selection signal when said first high breakdown voltage transistor is turned on, and said second high breakdown voltage transistor supplying a low internal power supply voltage to said means for generating a row selection signal when said second high breakdown voltage transistor is turned on.
Claim 10
Dependent Claim
139 words
A programmable read-only memory device according to claim 5, wherein said means for generating a row selection signal comprises: a gate circuit for decoding input row addresses, a first high breakdown voltage type transistor having a source connected to an output terminal of said gate circuit and having a gate which receives a power supply voltage, a CMIS inverter composed of high breakdown voltage MIS transistors, said inverter having an input terminal connected to the drain of said first high breakdown voltage type transistor and being supplied with said internal power supply voltages supplied from said second power switch circuit, and a second high breakdown voltage type transistor connected between said second power switch circuit and a drain of said first high breakdown voltage type transistor and having a gate which receives an output signal of said CMIS inverter.
Claim 11
Dependent Claim
137 words
A programmable read-only memory device according to claim 5, wherein said means for generating a column selection signal comprises: a gate circuit for decoding input column addreses, a first high breakdown voltage type transistor having a source connected to an output terminal of said gate circuit and a gate which receives a power supply voltage, a CMIS inverter composed of high breakdown voltage MIS transistors, said inverter having an input terminal to a drain of said first high breakdown voltage type transistor and being supplied with said internal power supply voltages supplied from said first power switch circuit, and a second high breakdown voltage type transistor connected between said first power switch circuit and a drain of said first high breakdown voltage type transistor and having a gate which receives an output signal of said CMIS inverter.
Claim 12
Dependent Claim
23 words
A programmable read-only memory device according to claim 5, wherein said delay means delays said program signal to generate said delayed program signal.
Claim 13
Dependent Claim
56 words
A programmable read-only memory device according to claim 10, wherein said delay means comprises an integrator circuit having an N-channel MIS transistor and a P-channel MIS transistor connected in parallel and inserted between an input terminal and an output terminal of said integrator circuit, and a capacitor connected between said output terminal and a power source.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-03-09 | 1990-09-08 | 1991-03-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-03-09 | 1994-09-08 | 1995-03-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-03-09 | 1998-09-08 | 1999-03-10 | $7700.00 | Window Closed / Lapsed |