Method of making planarized EPROM array

Claim 2

A process for fabricating an array of floating gate memory cells at a face of a semiconductor layer of a first conductivity type, comprising the steps of: forming a plurality of elongated spaced-apart parallel source/drain regions of a second conductivity type opposite the first conductivity type at the face; depositing a thick dielectric layer on the face;

Claim 3

forming a plurality of spaced-apart orifices through the thick dielectric layer to the face, each orifice exposing portions of two adjacent source/drain regions and extending across an exposed surface therebetween; forming a plurality of thin first gate insulators on the face in the orifices; forming a plurality of conductive floating gate electrodes in the orifices on respective first gate insulators, the combined thicknesses of a first gate insulator and a respective floating gate electrode approximating the thickness of the thick dielectric layer; forming a second gate insulator on the floating gate electrodes and the thick dielectric layer; and forming a plurality of conductive control electrodes on the second gate insulator over the floating gate electrodes.

Claim 4

forming a plurality of spaced-apart orifices through the thick dielectric layer to the face, each orifice exposing portions of two adjacent source/drain regions and extending across an exposed surface therebetween; forming a plurality of thin first gate insulators on the face in the orifices; forming a plurality of conductive floating gate electrodes in the orifices on respective first gate insulators, the combined thicknesses of a first gate insulator and a respective floating gate electrode approximating the thickness of the thick dielectric layer; forming a second gate insulator on the floating gate electrodes and the thick dielectric layer; and forming a plurality of conductive control electrodes on the second gate insulator over the floating gate electrodes.

Claim 5

The process of claim 1, wherein said step of forming the second gate insulator comprises the further steps of: forming a thin oxide layer on the floating gate electrodes and the first dielectric layer; and forming a thin nitride layer on the thin oxide layer.

Claim 6

The process of claim 2, and further including the steps of: removing the thin oxide and nitride layers from a peripheral area of the array; forming a peripheral gate oxide for transistors in the peripheral area; and using the nitride layer to passivate the structures therebeneath from said step of forming the peripheral gate oxide.

Claim 7

The process of claim 1, and further including the step of forming the floating gate electrodes from polycrystalline silicon.

Claim 8

The process of claim 1, and further comprising the step of annealing the source/drain regions prior to said step of depositing the thick dielectric layer.

Claim 9

The process of claim 1, wherein said step of forming the first gate insulator comprises growing a thin layer of oxide on the face inside each orifice.

Claim 10

The process of claim 6, and further including the step of forming the first gate insulator in each orifice to be thicker over the source/drain regions than over the exposed surface therebetween.

Claim 11

The process of claim 1, and further comprising the step of depositing the thick dielectric layer on the face by chemical vapor deposition such that the source/drain regions remain near the surface of the semiconductor layer.

Claim 12

The process of claim 1, wherein said step of forming the floating gate electrodes comprises the further steps of: depositing a conductive layer in the orifices and over the thick dielectric layer; and back-etching the conductive layer such that the conductive layer is removed from all areas except inside the orifices.

Claim 13

The process of claim 9, wherein said step of forming the floating gate electrodes comprises the further step of depositing a conductive layer in the orifices and over the thick dielectric layer to a sufficient thickness that the upper surface thereof is substantially planar.

Claim 14

The process of claim 9, wherein said step of forming the floating gate electrodes includes the further steps of: after depositing the conductive layer, differentially depositing a sacrificial layer such that the upper surface thereof will be planar; and back-etching the sacrificial layer and the conductive layer at substantially the same rate such that all of the conductive layer outside the orifices will be removed down to the surface of the thick dielectric layer.

Claim 15

A process for fabricating an array of electrically programmable read-only memory cells arranged in rows and in columns at an angle to the rows at a face of a semiconductor layer of a first conductivity type, comprising: implanting a plurality of elongate spaced parallel source/drain regions of a second conductivity type opposite the first conductivity type into the face, the source/drain regions oriented in a column direction; depositing a thick dielectric layer on the face; selectively etching a plurality of spaced-apart floating gate orifices through the thick dielectric layer to the face, the floating gate orifices aligned in the rows and columns, each floating gate orifice exposing portions of two source/drain regions; forming a thin gate dielectric layer on the face in each floating gate orifice; depositing a thick first conductor layer over the dielectric layers in sufficient thickness such that the first conductor layer has a substantially planar upper surface; etching the first conductor layer to remove all portions thereof outside the orifices such that an isolated floating gate is formed in each orifice having an upper surface substantially coplanar with the upper surface of the thick dielectric layer; forming a second thin dielectric layer over the thick dielectric layer and over the floating gates; and forming a plurality of elongate parallel conductive control electrodes on the second thin dielectric layer, each control electrode formed over a row of floating gates.

Claim 16

A process for fabricating an array of electrically programmable read-only memory cells arranged in rows and in columns at an angle to the rows at a face of a semiconductor layer of a first conductivity type, comprising: implanting a plurality of elongate spaced parallel source/drain regions of a second conductivity type opposite the first conductivity type into the face, the source/drain regions oriented in a column direction; depositing a thick dielectric layer on the face; selectively etching a plurality of spaced-apart floating gate orifices through the thick dielectric layer to the face, the floating gate orifices aligned in the rows and columns, each floating gate orifice exposing portions of two source/drain regions; forming a thin gate dielectric layer on the face in each floating gate orifice; depositing a thick first conductor layer over the dielectric layers in sufficient thickness such that the first conductor layer has a substantially planar upper surface; etching the first conductor layer to remove all portions thereof outside the orifices such that an isolated floating gate is formed in each orifice having an upper surface substantially coplanar with the upper surface of the thick dielectric layer; forming a second thin dielectric layer over the thick dielectric layer and over the floating gates; and forming a plurality of elongate parallel conductive control electrodes on the second thin dielectric layer, each control electrode formed over a row of floating gates.