Erase method for page mode multiple bits-per-cell flash EEPROM

Claim 1

An improved erasing structure for performing a programming back operation and a concurrent verify operation subsequent to application of an erasing pulse in an array of multiple bits-per-cell flash EEPROM memory cells on a more effective and efficient basis, said erasing structure comprising in combination: a memory core (12) having a plurality of memory cells arranged in rows of wordlines and columns of bit lines intersecting said rows of wordlines, each of said memory core cells including a floating gate array transistor having its control gate connected to one of said rows of wordlines, its drain/source connected to one of said columns of bit lines, and its source/drain connected to a common array ground line; means (17) for generating a control signal to control the rise-time of voltages on the wordlines; row decoder means (14) responsive to said control signals and row address signals and being operatively connected to said memory core array for selecting certain ones of said rows of word lines; column decoder means (16, 20) responsive to column address signals and being operatively connected to said memory core array for selecting certain ones of said columns of bit lines; erase verify reference cell array means (25) for generating an upper erased state threshold voltage level; erase verify decoder means (15) responsive to said control signal for controlling said erase verify reference cell array means; pre-charging means (36) for initially precharging all of said array bit lines to a predetermined potential prior to a programming back operation; reference generator means (134) for generating a reference output voltage corresponding to a lower erased state threshold voltage level; switching means (36a) for selectively disconnecting a program current source from the selected certain ones of said columns of bit lines containing the selected memory core cells which have been correctly programmed back; sensing logic means (26, 27) having a first input coupled to the reference output voltage of said reference voltage generator means and having a second input coupled to one of the selected certain ones of said columns of bit lines for continuously comparing a potential on the one of the selected bit lines and said reference output voltage corresponding to the lower erased state threshold voltage level; said sensing logic means having an output for generating a logic signal which is switched to a first logic level when said potential on said one of the selected bit lines falls below said reference output voltage corresponding to lower erased state threshold voltage level; and said switching means being responsive to said first logic level for disconnecting said program current source so as to inhibit further programming back of said selected memory core cells.