EP0373830A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Floating gate transistor
Assignee: Waferscale Integration Inc
•
Filing: 1989-12-08
•
Granted: —
•
Expires: 2009-12-08
Abstract
Abstract A floating gate transistor is programmed by a conventional charge pump providing drain programming current, typically held below about 1 µA. The drain current can be limited by connecting a resistor between the source and ground, or by limiting the transistor control gate voltage. Instead, a charge pump is coupled to the drain while the control gate is repetitively pulsed. Each time the control gate is pulsed, the transistor turns on, and although the drain is initially discharged through the transistor, some hot electrons are accelerated onto the floating gate, and eventually the floating gate is programmed. The erase gate voltage may be raised to enhance programming efficiency.
Inventors
- 👤 Reza Kazerounian
- 👤 Boaz Eitan
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 22:59
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/04; G11C16/0408; G11C16/0425; G11C16/30
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
100 words
A method of programming a floating gate transistor, the transistor comprising a source, a drain spaced apart from the source, the source and drain being of a first conductivity type and formed in a semiconductor region of a second conductivity type, a channel extending between the source and the drain, a floating gate extending over at least a portion of the channel, and a control gate extending over the floating gate, the method comprising the steps of: applying programming voltages to the drain and the control gate; and ensuring that the programming drain current is less than a predetermined value.
Claim 2
Independent Claim
100 words
A method of programming a floating gate transistor, the transistor comprising a source, a drain spaced apart from the source, the source and drain being of a first conductivity type and formed in a semiconductor region of a second conductivity type, a channel extending between the source and the drain, a floating gate extending over at least a portion of the channel, and a control gate extending over the floating gate, the method comprising the steps of: applying programming voltages to the drain and the control gate; and ensuring that the programming drain current is less than a predetermined value.
Claim 3
Dependent Claim
20 words
A method as claimed in claim 1 wherein the predetermined value is less than or equal to about 150 µA.
Claim 4
Dependent Claim
20 words
A method as claimed in claim 1 wherein the predetermined value is less than or equal to about 10 µA.
Claim 5
Dependent Claim
41 words
A method as claimed in claim 1 wherein the programming drain voltage is provided by a charge pump and the programming drain current is held to a value sufficiently low so that the charge pump can provide the programming drain current.
Claim 6
Dependent Claim
78 words
A method as claimed in claim 1 comprising the step of applying to the control gate a voltage which rises from a first value to a second value such that during the time the voltage at the control gate is rising, electrons are being injected into the floating gate so that the threshold voltage of the transistor increases at a rate which ensures that the transistor does not draw a drain current over the predetermined value during programming.
Claim 7
Dependent Claim
26 words
A method as claimed in claim 5 wherein the control gate rises from the first value to the second value over a 0.1 ms time period.
Claim 8
Dependent Claim
31 words
A method as claimed in claim 1 wherein the ensuring step comprises the step of applying a voltage to the control gate to keep the drain current below the predetermined value.
Claim 9
Dependent Claim
29 words
A method as claimed in claim 1 wherein the ensuring step comprises the step of providing an electrical resistance between the source and ground, the semiconductor region being grounded.
Claim 10
Independent Claim
71 words
A method of programming a floating gate transistor, the transistor comprising a source, a drain, a channel extending between the source and drain, a floating gate extending over at least a portion of the channel, and a control gate extending over at least a portion of the floating gate, the method comprising the steps of: coupling a programming voltage generator to the drain; and repetitively applying pulses to the control gate.
Claim 11
Independent Claim
71 words
A method of programming a floating gate transistor, the transistor comprising a source, a drain, a channel extending between the source and drain, a floating gate extending over at least a portion of the channel, and a control gate extending over at least a portion of the floating gate, the method comprising the steps of: coupling a programming voltage generator to the drain; and repetitively applying pulses to the control gate.
Claim 12
Dependent Claim
16 words
A method as claimed in claim 9 wherein the programming voltage generator is a charge pump.
Claim 13
Dependent Claim
64 words
A method as claimed in claim 9 or 10 wherein the programming voltage generator is incapable of generating an output current which the transistor would normally conduct if 1) the floating gate were unprogrammed, 2) the programming drain voltage was applied to the drain, and 3) a programming control gate voltage equal to the amplitude of the pulses was applied to the control gate.
Claim 14
Independent Claim
37 words
A method as claimed in any one of claims 7-11 wherein the transistor comprises an erase gate capacitively coupled to the floating gate, and the method comprises the step of raising the voltage of the erase gate.
Claim 15
Dependent Claim
21 words
A method as claimed in claim 12 wherein the voltage at the erase gate is greater than 5 volts during programming.
Claim 16
Dependent Claim
21 words
A method as claimed in claim 12 wherein the voltage at the erase gate is less than 20 volts during programming.
Claim 17
Independent Claim
24 words
A method as claimed in any one of claims 8 and 9-11 wherein the transistor comprises an erase gate which is grounded during programming.
Claim 18
Dependent Claim
97 words
A structure comprising a floating gate transistor, the transistor comprising a source, a drain spaced apart from the source, the source and the drain being of a first conductivity type and formed in a semiconductor region of a second conductivity type, a channel extending between the source and the drain, a floating gate extending over at least a portion of the channel, a control gate extending over the floating gate, means for applying programming voltages to the drain and the control gate, and means for ensuring that the programming drain current is less than a predetermined value.
Claim 19
Dependent Claim
97 words
A structure comprising a floating gate transistor, the transistor comprising a source, a drain spaced apart from the source, the source and the drain being of a first conductivity type and formed in a semiconductor region of a second conductivity type, a channel extending between the source and the drain, a floating gate extending over at least a portion of the channel, a control gate extending over the floating gate, means for applying programming voltages to the drain and the control gate, and means for ensuring that the programming drain current is less than a predetermined value.
Claim 20
Dependent Claim
65 words
A structure including a floating gate transistor, the transistor comprising a source, a drain, a channel extending between the source and drain, a floating gate extending over at least a portion of the channel, a control gate extending over at least a portion of the floating gate, a programming voltage generator coupled to the drain, and means for repeatedly applying pulses to the control gate.
Claim 21
Dependent Claim
65 words
A structure including a floating gate transistor, the transistor comprising a source, a drain, a channel extending between the source and drain, a floating gate extending over at least a portion of the channel, a control gate extending over at least a portion of the floating gate, a programming voltage generator coupled to the drain, and means for repeatedly applying pulses to the control gate.
Claim 22
Independent Claim
154 words
A method of manufacturing a floating gate transistor comprising the steps of: providing a structure comprising a first region of semiconductor material of a first conductivity type and a first dopant concentration, and a floating gate formed over but insulated from a portion of the first region; forming a source and drain having a second conductivity type within the first region, the drain being spaced apart from the source so that a channel extends between the source and the drain and so that the floating gate extends over a first part of the channel but not a second part of the channel; introducing dopants of the second conductivity type into a second portion of the channel to partially counter-dope the second portion, thereby forming a second region of semiconductor material having a net dopant concentration less than the first dopant concentration; and forming a control gate over the floating gate and the second portion.
Claim 23
Independent Claim
154 words
A method of manufacturing a floating gate transistor comprising the steps of: providing a structure comprising a first region of semiconductor material of a first conductivity type and a first dopant concentration, and a floating gate formed over but insulated from a portion of the first region; forming a source and drain having a second conductivity type within the first region, the drain being spaced apart from the source so that a channel extends between the source and the drain and so that the floating gate extends over a first part of the channel but not a second part of the channel; introducing dopants of the second conductivity type into a second portion of the channel to partially counter-dope the second portion, thereby forming a second region of semiconductor material having a net dopant concentration less than the first dopant concentration; and forming a control gate over the floating gate and the second portion.
Claim 24
Dependent Claim
26 words
A method as claimed in claim 18 wherein the step of introducing dopants is accomplished so that the second region is self-aligned with the floating gate.
Claim 25
Dependent Claim
214 words
A staggered split gate floating gate memory array comprising: a region of semiconductor material of a first conductivity type; a plurality of elongate mutually parallel source/drain regions (204a-204c) of a second conductivity type formed in the region of semiconductor material; a plurality of groups of floating gates (202a-202d), each group of floating gates being formed between an associated pair of source/drain regions (204a,204b), wherein a first set of floating gates (202a,202b) within each group is formed adjacent to a first one of the source/drain regions (204a) within the pair but does not extend to a second one of the source/drain regions (204b) within the pair, and wherein a second set of floating gates (202c,202d) within each group is formed adjacent the second source/drain region (204b) but does not extend to the first source/drain region (204a); a plurality of control gates (206a,206b), each control gate extending in a direction perpendicular to the source/drain regions, each control gate extending over a first portion of an associated column of floating gates but not a second portion of the associated column of floating gates; and a plurality of erase gates (208a,208b) extending in a direction parallel to the control gates, each erase gate extending over the second portion of an associated pair of columns of the floating gates.
Claim 26
Dependent Claim
214 words
A staggered split gate floating gate memory array comprising: a region of semiconductor material of a first conductivity type; a plurality of elongate mutually parallel source/drain regions (204a-204c) of a second conductivity type formed in the region of semiconductor material; a plurality of groups of floating gates (202a-202d), each group of floating gates being formed between an associated pair of source/drain regions (204a,204b), wherein a first set of floating gates (202a,202b) within each group is formed adjacent to a first one of the source/drain regions (204a) within the pair but does not extend to a second one of the source/drain regions (204b) within the pair, and wherein a second set of floating gates (202c,202d) within each group is formed adjacent the second source/drain region (204b) but does not extend to the first source/drain region (204a); a plurality of control gates (206a,206b), each control gate extending in a direction perpendicular to the source/drain regions, each control gate extending over a first portion of an associated column of floating gates but not a second portion of the associated column of floating gates; and a plurality of erase gates (208a,208b) extending in a direction parallel to the control gates, each erase gate extending over the second portion of an associated pair of columns of the floating gates.
References Cited (Backward Citations)
GB2094086A
Cited
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.