Patent US7476586B2 successfully refreshed from Google Patents.
US7476586B2
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US
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NOR flash memory cell with high storage density
Assignee: Micron Technology Inc
•
Filing: 2006-07-20
•
Granted: 2009-01-13
•
Expires: 2026-07-20
Abstract
Abstract Structures and methods for NOR flash memory cells, arrays and systems are provided. The NOR flash memory cell includes a vertical floating gate transistor extending outwardly from a substrate. The floating gate transistor having a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, a floating gate separated from the channel region by a gate insulator, and a control gate separated from the floating gate by a gate dielectric. A sourceline is formed in a trench adjacent to the vertical floating gate transistor and coupled to the first source/drain region. A transmission line coupled to the second source/drain region. And, a wordline is coupled to the control gate perpendicular to the sourceline.
Inventors
- 👤 Leonard Forbes
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 08:42
CPC Classifications
H; H10; H10B; H10B69/00; G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0416; H10B41/00; H10B41/20; H10B41/23; H10B41/27; H10B41/30; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0411; H10D30/60; H10D30/68; H10D30/681; H10D30/684; H10D30/685; H10D30/686; G11C2216/00; G11C2216/12; G11C2216/28
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
147 words
A method for forming a NOR flash memory cell, comprising: forming a vertical floating gate transistor from a vertical pillar extending outwardly from a substrate, the floating gate transistor having a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, a floating gate separated from the channel region by a gate insulator, and a control gate separated from the floating gate by a gate dielectric; forming a sourceline in a trench adjacent to the vertical floating gate transistor; coupling the first source/drain region to the sourceline; coupling a transmission line to the second source/drain region; and coupling circuitry to the source/drain regions to store a charge in the floating gate in a first direction such that the programmed floating gate transistor operates at reduced drain source current when read in a second direction opposite from the first direction.
Claim 2
Independent Claim
147 words
A method for forming a NOR flash memory cell, comprising: forming a vertical floating gate transistor from a vertical pillar extending outwardly from a substrate, the floating gate transistor having a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, a floating gate separated from the channel region by a gate insulator, and a control gate separated from the floating gate by a gate dielectric; forming a sourceline in a trench adjacent to the vertical floating gate transistor; coupling the first source/drain region to the sourceline; coupling a transmission line to the second source/drain region; and coupling circuitry to the source/drain regions to store a charge in the floating gate in a first direction such that the programmed floating gate transistor operates at reduced drain source current when read in a second direction opposite from the first direction.
Claim 3
Dependent Claim
26 words
The method of claim 1 , wherein forming each floating gate includes forming each floating gate in a trench below a top surface of the pillar.
Claim 4
Dependent Claim
27 words
The method of claim 1 , wherein forming the floating gate includes forming a vertically oriented floating gate having a vertical length of less than 100 nanometers.
Claim 5
Dependent Claim
41 words
The method of claim 1 , wherein forming a vertical floating gate transistor includes forming a pair of floating gates within a trench, and wherein forming a control gate includes forming a single control gate over the pair of floating gates.
Claim 6
Dependent Claim
39 words
The method of claim 1 , wherein forming a vertical floating gate transistor includes forming a pair of floating gates within a trench, and wherein a pair of control gates is formed over the pair of floating gates respectively.
Claim 7
Dependent Claim
33 words
The method of claim 1 , wherein forming the vertical floating gate transistor includes forming a vertical floating gate transistor having a size of approximately 2.0 lithographic features squared (2 F 2 ).
Claim 8
Independent Claim
145 words
A method for forming a NOR flash memory cell, comprising: forming a vertical floating gate transistor from a vertical pillar extending outwardly from a substrate, the floating gate transistor having a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, a floating gate separated from the channel region by a gate insulator, and a control gate separated from the floating gate by a gate dielectric; forming a sourceline in a trench adjacent to the vertical floating gate transistor; coupling the first source/drain region to the sourceline; coupling a bitline to the second source/drain region; and wherein the NOR flash memory cell is configured to program in a reverse direction to trap a charge in the floating gate, such that the programmed floating gate transistor operates at reduced drain source current when read in a forward direction.
Claim 9
Independent Claim
145 words
A method for forming a NOR flash memory cell, comprising: forming a vertical floating gate transistor from a vertical pillar extending outwardly from a substrate, the floating gate transistor having a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, a floating gate separated from the channel region by a gate insulator, and a control gate separated from the floating gate by a gate dielectric; forming a sourceline in a trench adjacent to the vertical floating gate transistor; coupling the first source/drain region to the sourceline; coupling a bitline to the second source/drain region; and wherein the NOR flash memory cell is configured to program in a reverse direction to trap a charge in the floating gate, such that the programmed floating gate transistor operates at reduced drain source current when read in a forward direction.
Claim 10
Dependent Claim
26 words
The method of claim 7 , wherein forming each floating gate includes forming each floating gate in a trench below a top surface of the pillar.
Claim 11
Dependent Claim
41 words
The method of claim 7 , wherein forming a vertical floating gate transistor includes forming a pair of floating gates within a trench, and wherein forming a control gate includes forming a single control gate over the pair of floating gates.
Claim 12
Dependent Claim
39 words
The method of claim 7 , wherein forming a vertical floating gate transistor includes forming a pair of floating gates within a trench, and wherein a pair of control gates is formed over the pair of floating gates respectively.
Claim 13
Independent Claim
178 words
A method for forming a NOR flash memory cell, comprising: forming a vertical floating gate transistor from a vertical pillar extending outwardly from a substrate, the floating gate transistor having a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, a floating gate separated from the channel region by a gate insulator, and a control gate separated from the floating gate by a gate dielectric, wherein the control gate is a common control gate shared by the floating gate and a second floating gate of a reference transistor located on an opposite side of a trench; forming a sourceline in the trench adjacent to the vertical floating gate transistor; coupling the first source/drain region to the sourceline; coupling a transmission line to the second source/drain region; and coupling circuitry to the source/drain regions to store a charge in the floating gate in a first direction such that the programmed floating gate transistor operates at reduced drain source current when read in a second direction opposite from the first direction.
Claim 14
Independent Claim
178 words
A method for forming a NOR flash memory cell, comprising: forming a vertical floating gate transistor from a vertical pillar extending outwardly from a substrate, the floating gate transistor having a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, a floating gate separated from the channel region by a gate insulator, and a control gate separated from the floating gate by a gate dielectric, wherein the control gate is a common control gate shared by the floating gate and a second floating gate of a reference transistor located on an opposite side of a trench; forming a sourceline in the trench adjacent to the vertical floating gate transistor; coupling the first source/drain region to the sourceline; coupling a transmission line to the second source/drain region; and coupling circuitry to the source/drain regions to store a charge in the floating gate in a first direction such that the programmed floating gate transistor operates at reduced drain source current when read in a second direction opposite from the first direction.
Claim 15
Dependent Claim
33 words
The method of claim 11 , wherein forming a sourceline in a trench includes forming a common sourceline in the trench coupled to both the vertical floating gate transistor and the reference transistor.
Claim 16
Dependent Claim
17 words
The method of claim 12 , wherein forming the sourceline includes implanting a dopant into the trench.
Claim 17
Dependent Claim
27 words
The method of claim 11 , wherein forming a vertical floating gate transistor includes forming a control gate between a pair of floating gates in the trench.
Claim 18
Independent Claim
238 words
A method for forming a NOR flash memory cell, comprising: forming a first vertical floating gate transistor from a vertical pillar extending outwardly from a substrate, the first floating gate transistor having a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, a first floating gate separated from the channel region by a gate insulator, and a first control gate separated from the floating gate by a gate dielectric; forming a second vertical floating gate reference transistor from an adjacent vertical pillar extending outwardly from the substrate, the second floating gate reference transistor having a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, a second floating gate separated from the channel region by a gate insulator, and a second control gate separated from the second floating gate by a gate dielectric; wherein the first floating gate, the second floating gate, the first control gate, and the second control gate are all located in a trench between vertical pillars; coupling the first source/drain regions to a common sourceline; coupling a transmission line to the second source/drain regions; and coupling circuitry to the source/drain regions to store a charge in the floating gate in a first direction such that the programmed floating gate transistor operates at reduced drain source current when read in a second direction opposite from the first direction.
Claim 19
Independent Claim
238 words
A method for forming a NOR flash memory cell, comprising: forming a first vertical floating gate transistor from a vertical pillar extending outwardly from a substrate, the first floating gate transistor having a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, a first floating gate separated from the channel region by a gate insulator, and a first control gate separated from the floating gate by a gate dielectric; forming a second vertical floating gate reference transistor from an adjacent vertical pillar extending outwardly from the substrate, the second floating gate reference transistor having a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, a second floating gate separated from the channel region by a gate insulator, and a second control gate separated from the second floating gate by a gate dielectric; wherein the first floating gate, the second floating gate, the first control gate, and the second control gate are all located in a trench between vertical pillars; coupling the first source/drain regions to a common sourceline; coupling a transmission line to the second source/drain regions; and coupling circuitry to the source/drain regions to store a charge in the floating gate in a first direction such that the programmed floating gate transistor operates at reduced drain source current when read in a second direction opposite from the first direction.
Claim 20
Dependent Claim
22 words
The method of claim 15 , further including forming the common sourceline by implanting a dopant into a base of the trench.
Claim 21
Dependent Claim
31 words
The method of claim 15 , wherein the first control gate, and the second control gate are located above the first floating gate and the second floating gate within the trench.
Claim 22
Dependent Claim
31 words
The method of claim 15 , wherein the first control gate, and the second control gate are located between the first floating gate and the second floating gate within the trench.
Claim 23
Independent Claim
204 words
A method for forming a NOR flash memory cell, comprising: forming a first vertical floating gate transistor from a vertical pillar extending outwardly from a substrate, the first floating gate transistor having a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions; forming a second vertical floating gate reference transistor from an adjacent vertical pillar extending outwardly from the substrate, the second floating gate reference transistor having a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions; forming a single shared floating gate in a trench between the channel regions of the first vertical floating gate transistor and the second vertical floating gate reference transistor; forming a single shared control gate within the trench, separated from the single shared floating gate by an insulator layer; coupling the first source/drain regions to a common sourceline; coupling a transmission line to the second source/drain regions; and coupling circuitry to the source/drain regions to store a charge in the floating gate in a first direction such that the programmed floating gate transistor operates at reduced drain source current when read in a second direction opposite from the first direction.
Claim 24
Independent Claim
204 words
A method for forming a NOR flash memory cell, comprising: forming a first vertical floating gate transistor from a vertical pillar extending outwardly from a substrate, the first floating gate transistor having a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions; forming a second vertical floating gate reference transistor from an adjacent vertical pillar extending outwardly from the substrate, the second floating gate reference transistor having a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions; forming a single shared floating gate in a trench between the channel regions of the first vertical floating gate transistor and the second vertical floating gate reference transistor; forming a single shared control gate within the trench, separated from the single shared floating gate by an insulator layer; coupling the first source/drain regions to a common sourceline; coupling a transmission line to the second source/drain regions; and coupling circuitry to the source/drain regions to store a charge in the floating gate in a first direction such that the programmed floating gate transistor operates at reduced drain source current when read in a second direction opposite from the first direction.
Claim 25
Dependent Claim
28 words
The method of claim 19 , wherein forming the floating gate includes forming a floating gate having a vertical height within the trench of less than 100 nanometers.
Claim 26
Dependent Claim
22 words
The method of claim 19 , further including forming the common sourceline by implanting a dopant into a base of the trench.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2012-01-13 | 2012-07-14 | 2013-01-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2016-01-13 | 2016-07-14 | 2017-01-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2020-01-13 | 2020-07-14 | 2021-01-13 | $7700.00 | Window Closed / Lapsed |