Patent US7329923B2 successfully refreshed from Google Patents.
US7329923B2
Expired / Lapsed
US
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High-performance CMOS devices on hybrid crystal oriented substrates
Assignee: International Business Machines Corp
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Filing: 2003-06-17
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Granted: 2008-02-12
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Expires: 2023-06-17
Abstract
Abstract An integrated semiconductor structure containing at least one device formed upon a first crystallographic surface that is optimal for that device, while another device is formed upon a second different crystallographic surface that is optimal for the other device is provided. The method of forming the integrated structure includes providing a bonded substrate including at least a first semiconductor layer of a first crystallographic orientation and a second semiconductor layer of a second different crystallographic orientation. A portion of the bonded substrate is protected to define a first device area, while another portion of the bonded substrate is unprotected. The unprotected portion of the bonded substrate is then etched to expose a surface of the second semiconductor layer and a semiconductor material is regrown on the exposed surface. Following planarization, a first semiconductor device is formed in the first device region and a second semiconductor device is formed on the regrown material.
Inventors
- 👤 Bruce B. Doris
- 👤 Kathryn W. Guarini
- 👤 Meikei Ieong
- 👤 Shreesh Narasimha
- 👤 Kern Rim
- 👤 Jeffrey W. Sleight
- 👤 Min Yang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 08:54
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10P; H10P90/00; H10P90/19; H10P90/1904; H10P90/1906; H10P90/1914; H10D84/0167; H10D84/02; H10D84/03; H10D84/038; H10D86/00; H10D86/01; H10W; H10W10/00; H10W10/01; H10W10/061; H10W10/10; H10W10/181
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
152 words
An integrated semiconductor structure comprising: a substrate comprising a first surface region having a first surface orientation and a second surface region having a second surface orientation, said first surface orientation is different from said second surface orientation and said first and second surface regions are substantially planar to each other; and at least one first semiconductor device located on said first surface region and at least one second semiconductor device located on said second surface region, wherein a buried insulating layer is located beneath one of said first or second surface regions and at least one of said first or second surface regions includes a regrown semiconductor material that extends down to an underlying semiconductor layer that is located beneath said buried insulating layer, wherein said regrown semiconductor material and said underlying semiconductor layer have a same crystallographic orientation, and wherein said first and second semiconductor regions both include strained Si.
Claim 2
Dependent Claim
152 words
An integrated semiconductor structure comprising: a substrate comprising a first surface region having a first surface orientation and a second surface region having a second surface orientation, said first surface orientation is different from said second surface orientation and said first and second surface regions are substantially planar to each other; and at least one first semiconductor device located on said first surface region and at least one second semiconductor device located on said second surface region, wherein a buried insulating layer is located beneath one of said first or second surface regions and at least one of said first or second surface regions includes a regrown semiconductor material that extends down to an underlying semiconductor layer that is located beneath said buried insulating layer, wherein said regrown semiconductor material and said underlying semiconductor layer have a same crystallographic orientation, and wherein said first and second semiconductor regions both include strained Si.
Claim 3
Dependent Claim
25 words
The integrated semiconductor structure of claim 1 wherein the first surface orientation is a (110) orientation and the second surface orientation is a (100) orientation.
Claim 4
Dependent Claim
29 words
The integrated semiconductor structure of claim 2 wherein said at least one first semiconductor device is a PFET and the at least one second semiconductor device is an NFET.
Claim 5
Dependent Claim
26 words
The integrated semiconductor structure of claim 1 wherein said regrown semiconductor material comprises a strained Si layer located atop a relaxed SiGe alloy or SiC alloy.
Claim 6
Dependent Claim
21 words
The integrated semiconductor structure of claim 1 further comprising an isolation region separating said first and second regions from each other.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2011-02-11 | 2011-08-13 | 2012-02-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2015-02-11 | 2015-08-13 | 2016-02-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2019-02-11 | 2019-08-13 | 2020-02-12 | $7700.00 | Window Closed / Lapsed |