US6531369B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Heterojunction bipolar transistor (HBT) fabrication using a selectively deposited silicon germanium (SiGe)
Assignee: Qualcomm Inc
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Filing: 2002-02-14
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Granted: 2003-03-11
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Expires: 2022-02-14
Abstract
Abstract A Heterojunction Bipolar Transistor (HBT) is provided where the SiGe base region is formed through selective deposition, after the formation of the base electrode layer and the emitter window. A sacrificial oxide layer is deposited between the collector and base electrode. The contact to the SiGe base is made at an extrinsic area, underneath the base electrode, after removal of the sacrificial oxide. The SiGe is covered with a temporary oxide layer during further processes, and this protective layer is removed immediately before the deposition of the emitter material. The selective deposition of the SiGe at a relatively late stage of the fabrication process helps insure that the film remains free of the stresses which can degrade electron mobility. A process of fabricating the above-described HBT device is also provided.
Inventors
- 👤 Cengiz S. Ozkan
- 👤 Abderrahmane Salmi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 04:10
CPC Classifications
H; H10; H10D; H10D10/00; H10D10/01; H10D10/021; H10D10/80; H10D10/821; H10D10/891
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
109 words
A method for fabricating a Heterojunction Bipolar Transistor (HBT) comprising: providing a lightly doped silicon collector region; depositing a silicon bottom cap layer to separate the collector region from a base region; selectively depositing a silicon germanium (SiGe) composition to form the base region; depositing a silicon top cap layer overlying the SiGe base region, forming a base region top surface; forming a protective layer of oxide overlying the base region top surface, including oxidizing the silicon top cap layer; forming dielectric sidewalls to define an emitter region; etching to remove the protective oxide layer overlying the base region top surface; and forming an emitter overlying the base region.
Claim 2
Independent Claim
109 words
A method for fabricating a Heterojunction Bipolar Transistor (HBT) comprising: providing a lightly doped silicon collector region; depositing a silicon bottom cap layer to separate the collector region from a base region; selectively depositing a silicon germanium (SiGe) composition to form the base region; depositing a silicon top cap layer overlying the SiGe base region, forming a base region top surface; forming a protective layer of oxide overlying the base region top surface, including oxidizing the silicon top cap layer; forming dielectric sidewalls to define an emitter region; etching to remove the protective oxide layer overlying the base region top surface; and forming an emitter overlying the base region.
Claim 3
Dependent Claim
66 words
The method of claim 1 further comprising: preceding the selective SiGe deposition, forming a gate oxide layer; depositing a sacrificial layer of oxide overlying the gate oxide layer; depositing a layer of silicon overlying the sacrificial layer of oxide, forming a base electrode; depositing a layer of nitride overlying the silicon layer; and depositing a layer of TEOS overlying the nitride layer, forming a TEOS/nitride/silicon stack.
Claim 4
Dependent Claim
66 words
The method of claim 2 further comprising: patterning an emitter window in the TEOS/nitride/silicon stack; in which the formation of the dielectric sidewalls includes forming first nitride sidewalls adjoining the TEOS/nitride/silicon stack, following the patterning of the emitter window in the TEOS/nitride/silicon stack; and further comprising: etching the sacrificial oxide layer to form an undercut between the underlying silicon collector region and the overlying base electrode.
Claim 5
Dependent Claim
50 words
The method of claim 3 in which the selective deposition of SiGe includes using a chemistry selected from the group consisting of dichlorosilane (DCS) and DCS/Cl 2 to fill the undercut formed between the silicon collector region and the base electrode, forming an extrinsic contact with the overlying silicon layer.
Claim 6
Dependent Claim
23 words
The method of claim 4 in which the selective deposition of SiGe includes forming a base region with areas having no Ge content.
Claim 7
Dependent Claim
26 words
The method of claim 4 in which the selective deposition of SiGe includes forming a SiGe base region that is graded with respect to Ge content.
Claim 8
Dependent Claim
21 words
The method of claim 6 in which the selective deposition of SiGe includes the Ge content varying from 20% to 0%.
Claim 9
Dependent Claim
51 words
The method of claim 7 wherein the SiGe base region has a SiGe bottom surface adjacent the collector and a SiGe top surface, and in which the selective deposition of SiGe includes progressively varying the Ge content from 12% at the SiGe bottom surface to 0% at the SiGe top surface.
Claim 10
Dependent Claim
48 words
The method of claim 4 in which the formation of the protective oxide layer overlying the base region top surface includes oxidizing the base region top surface at a temperature in the range of 600 to 700 degrees C., and a pressure in the range of 10-25 atmospheres.
Claim 11
Dependent Claim
29 words
The method of claim 9 in which oxidizing the base region top surface includes oxidizing a layer having a thickness in the range of 50 to 250 Angstroms (Å).
Claim 12
Dependent Claim
34 words
The method of claim 4 in which the formation of the protective oxide layer overlying the base region top surface includes depositing a thin layer of oxide through a chemical vapor deposition (CVD) process.
Claim 13
Dependent Claim
44 words
The method of claim 4 in which the formation of dielectric sidewalls includes: isotropically depositing a sidewall oxide layer; isotropically depositing a second nitride sidewall layer, forming a nitride/oxide stack; and anisotropically etching the nitride/oxide stack to form an emitter opening with nitride/oxide sidewalls.
Claim 14
Dependent Claim
39 words
The method of claim 12 in which the formation of the emitter includes: depositing silicon in the emitter well overlying the base region top surface; implanting dopant in the emitter silicon; annealing; and forming contacts to the base electrode.
Claim 15
Dependent Claim
24 words
The method of claim 1 in which the selectively deposited SiGe is deposited to a thickness in the range of 500 to 1000 Å.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2006-03-10 | 2006-09-09 | 2007-03-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-03-10 | 2010-09-09 | 2011-03-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-03-10 | 2014-09-09 | 2015-03-11 | $7700.00 | Window Closed / Lapsed |