US5804487A
Expired / Lapsed
US
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Method of fabricating high βHBT devices
Assignee: Northrop Grumman Systems Corp
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Filing: 1996-07-10
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Granted: 1998-09-08
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Expires: 2016-07-10
Abstract
Abstract A method for controlling the spacing between the emitter mesa and the base ohmic metal of a heterojunction bipolar transistor (HBT) to obtain a relatively high gain (β) with a low-parasitic base resistance. In a first method, after the emitter, base and collector layers are epitaxially grown on a substrate, a sacrificial layer is deposited on top of the emitter layer. The emitter mesa is patterned with a photoresist using conventional lithography. Subsequently, the sacrificial layer is etched to produce an undercut. The emitter layer is then etched and a photoresist is applied over the first photoresist used to pattern the emitter mesa, as well as the entire device. The top layer of photoresist is patterned with a conventional process for lift-off metalization, such that the final resist profile has a re-entrant slope. The base ohmic metal is deposited and then lifted off by dissolving both the second layer of photoresist, as well as the original photoresist over the emitter mesa. The sacrificial layer is stripped using an isotropic etch leaving a base ohmic metal region surrounding an emitter mesa at a spacing that is determined by the initial undercut of the sacrificial layer. In an alternate embodiment of the invention, a method is disclosed for controlling the spacing between the base ohmic metal and an emitter ohmic metal.
Inventors
- 👤 Michael D. Lammert
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 11:17
CPC Classifications
H; H10; H10D; H10D10/00; H10D10/01; H10D10/021; H10P; H10P10/00; Y; Y10; Y10S; Y10S148/00; Y10S148/072; Y10S148/10; Y10S438/00; Y10S438/926; Y10S438/942; Y10S438/944; Y10S438/945; Y10S438/948; Y10S438/951
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
190 words
A method for aligning a metal and an emitter mesa, on an integrated circuit formed with a substrate and a plurality of vertically stacked epitaxial layers thereupon, defining a top exitaxial layer, the emitter mesa being disposed on top of the epitaxial layers, the method comprising the steps of: (a) depositing a layer of material on said top epitaxial layer; (b) depositing a first photoresist on said top epitaxial layer and said emitter mesa; (c) patterning and developing said first photoresist to define an emitter mesa on said top epitaxial layer; (d) etching said material to produce an undercut; (e) etching said top epitaxial layer to form said object; (f) depositing a second photoresist on said top exitaxial layer and said emitter mesa; (g) patterning and developing said second photoresist on said integrated circuit to define a re-entrant slope relative to said emitter mesa; (h) depositing a metal on said integrated circuit to form an ohmic contact; and (i) lifting off said metal, as well as said first photoresist and said second photoresist leaving an metal region around said emitter mesa that is uniformly spaced relative to said emitter mesa.
Claim 2
Independent Claim
190 words
A method for aligning a metal and an emitter mesa, on an integrated circuit formed with a substrate and a plurality of vertically stacked epitaxial layers thereupon, defining a top exitaxial layer, the emitter mesa being disposed on top of the epitaxial layers, the method comprising the steps of: (a) depositing a layer of material on said top epitaxial layer; (b) depositing a first photoresist on said top epitaxial layer and said emitter mesa; (c) patterning and developing said first photoresist to define an emitter mesa on said top epitaxial layer; (d) etching said material to produce an undercut; (e) etching said top epitaxial layer to form said object; (f) depositing a second photoresist on said top exitaxial layer and said emitter mesa; (g) patterning and developing said second photoresist on said integrated circuit to define a re-entrant slope relative to said emitter mesa; (h) depositing a metal on said integrated circuit to form an ohmic contact; and (i) lifting off said metal, as well as said first photoresist and said second photoresist leaving an metal region around said emitter mesa that is uniformly spaced relative to said emitter mesa.
Claim 3
Dependent Claim
16 words
A method as recited in claim 1, wherein said layer of material is a sacrificial layer.
Claim 4
Dependent Claim
17 words
A method as recited in claim 2, wherein said layer of said material is a dielectric film.
Claim 5
Dependent Claim
30 words
A method as recited in claim 1, wherein said dielectric film is selected from the group of Si 3 N 4 , SiO 2 and Al 2 O 3 .
Claim 6
Dependent Claim
18 words
A method as recited in claim 1, wherein said layer of said material is an ohmic metal layer.
Claim 7
Dependent Claim
21 words
A method as recited in claim 5, wherein said material is selected from the group of Ti, TiW, W and TiN.
Claim 8
Independent Claim
227 words
A method for aligning a base metal relative to an emitter mesa on a heterojunction bipolar transistor (HBT) having a substrate and a plurality of vertically stacked epitaxial layers thereupon including a base layer, a collector layer and an emitter layer, said emitter layer being formed on top, the method comprising the steps of: (a) depositing a sacrificial layer on top of said emitter layer; (b) depositing a first photoresist on top of said sacrificial layer; (c) patterning and developing a first photoresist on top of said sacrificial layer to form an emitter mesa; (d) etching said sacrificial layer to form an undercut; (e) etching said emitter layer to form said emitter mesa and expose a portion of said base layer; (f) depositing a second photoresist over said first photoresist and said base layer; (g) patterning and developing a second photoresist over said first photoresist and said exposed portion of said base layer with a re-entrant slope adjacent said exposed portion of said base layer; (h) depositing a base metal on said first photoresist, said second photoresist and said exposed portion of said base layer; and (i) lifting off said base metal deposited on said first and second photoresists along with said first and second photoresists leaving a base metal region around the emitter mesa whose spacing therefrom is determined by the undercut in said sacrificial layer.
Claim 9
Independent Claim
227 words
A method for aligning a base metal relative to an emitter mesa on a heterojunction bipolar transistor (HBT) having a substrate and a plurality of vertically stacked epitaxial layers thereupon including a base layer, a collector layer and an emitter layer, said emitter layer being formed on top, the method comprising the steps of: (a) depositing a sacrificial layer on top of said emitter layer; (b) depositing a first photoresist on top of said sacrificial layer; (c) patterning and developing a first photoresist on top of said sacrificial layer to form an emitter mesa; (d) etching said sacrificial layer to form an undercut; (e) etching said emitter layer to form said emitter mesa and expose a portion of said base layer; (f) depositing a second photoresist over said first photoresist and said base layer; (g) patterning and developing a second photoresist over said first photoresist and said exposed portion of said base layer with a re-entrant slope adjacent said exposed portion of said base layer; (h) depositing a base metal on said first photoresist, said second photoresist and said exposed portion of said base layer; and (i) lifting off said base metal deposited on said first and second photoresists along with said first and second photoresists leaving a base metal region around the emitter mesa whose spacing therefrom is determined by the undercut in said sacrificial layer.
Claim 10
Dependent Claim
15 words
The method as recited in claim 7, wherein said sacrificial layer is a dielectric film.
Claim 11
Dependent Claim
30 words
The method as recited in claim 8, wherein said dielectric film is selected from the group of Si 3 N 4 , SiO 2 and Al 2 O 3 .
Claim 12
Dependent Claim
15 words
The method as recited in claim 7, wherein said sacrificial layer is an organic film.
Claim 13
Dependent Claim
15 words
The method as recited in claim 7, wherein said sacrificial layer is a metal film.
Claim 14
Dependent Claim
17 words
The method as recited in claim 7, wherein said etching of said sacrificial layer is isotropic etching.
Claim 15
Dependent Claim
20 words
The method as recited in claim 7, wherein said etching of said sacrificial layer is combined isotropic and anisotropic etching.
Claim 16
Dependent Claim
17 words
The method as recited in claim 7, wherein said etching of said emitter layer includes isotropic etching.
Claim 17
Independent Claim
221 words
A method for aligning a base metal relative to an emitter mesa on a heterojunction bipolar transistor having a substrate and a plurality of vertically stacked epitaxial layers thereupon including a base layer, a collector layer and an emitter layer, the method comprising the steps of: (a) depositing an emitter metal on top of said emitter layer; (b) depositing a first photoresist on top of said emitter layer and said emitter metal; (c) patterning and developing said first photoresist on top of said emitter metal to form an emitter mesa; (d) etching said emitter metal to form an undercut; (e) etching said emitter layer to form said emitter mesa and exposing a portion of said base layer; (f) depositing a second photoresist on said emitter mesa and said base layer; (g) patterning said second photoresist over said first photoresist and said exposed portion of said base layer with a re-entrant slope adjacent said exposed portion of said base layer; (h) depositing a base metal on said first photoresist, said second photoresist and said exposed portion of said base layer; and (i) lifting off said base metal deposited on said first and second photoresists along with said first and second photoresists leaving a base metal region around the emitter mesa whose spacing therefrom is determined by the undercut in said emitter metal.
Claim 18
Independent Claim
221 words
A method for aligning a base metal relative to an emitter mesa on a heterojunction bipolar transistor having a substrate and a plurality of vertically stacked epitaxial layers thereupon including a base layer, a collector layer and an emitter layer, the method comprising the steps of: (a) depositing an emitter metal on top of said emitter layer; (b) depositing a first photoresist on top of said emitter layer and said emitter metal; (c) patterning and developing said first photoresist on top of said emitter metal to form an emitter mesa; (d) etching said emitter metal to form an undercut; (e) etching said emitter layer to form said emitter mesa and exposing a portion of said base layer; (f) depositing a second photoresist on said emitter mesa and said base layer; (g) patterning said second photoresist over said first photoresist and said exposed portion of said base layer with a re-entrant slope adjacent said exposed portion of said base layer; (h) depositing a base metal on said first photoresist, said second photoresist and said exposed portion of said base layer; and (i) lifting off said base metal deposited on said first and second photoresists along with said first and second photoresists leaving a base metal region around the emitter mesa whose spacing therefrom is determined by the undercut in said emitter metal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-09-07 | 2002-03-09 | 2002-09-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-09-07 | 2006-03-09 | 2006-09-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-09-07 | 2010-03-09 | 2010-09-08 | $7700.00 | Window Closed / Lapsed |