Fabrication of vertical SiGe base HBT with lateral collector contact on thin SOI

Claim 1

A method for forming a vertical heterojunction bipolar transistor having a lateral connector contact, comprising: 1) providing a silicon on insulator (SOI) substrate; 2) placing an epitaxial layer on the substrate, the epitaxial layer comprising a collector layer, a base layer above the collector layer and an emitter layer above the base layer; 3) etching away all but a portion of the epitaxial layer and of the silicon layer of the SOI substrate down to the oxide layer of the SOI substrate, the portion of the epitaxial layer constituting a device region; 4) forming a first dielectric sidewall spacer adjacent the device region and the portion of the silicon layer; 5) depositing a polysilicon layer having a dielectric film thereon on the device region, the first dielectric sidewall spacer and the SOI substrate, and etching the dielectric film and the polysilicon layer to leave a stripe of the polysilicon with dielectric on top, the stripe overhanging at least two edges of the device region; 6) etching away an exposed portion of the device region to expose a portion of an upper surface of the silicon layer of the SOI substrate, and doping the exposed upper surface to form a collector contact link; 7) forming a second dielectric sidewall spacer adjacent the stripe, the second dielectric sidewall spacer abutting the device region and the polysilicon layer on one side of the stripe, the second dielectric sidewall spacer abutting the polysilicon layer on an opposite side of the stripe; 8) forming a collector contact on the silicon of the SOI substrate adjacent the one wall of the stripe; 9) forming a base contact on the device region adjacent the opposite wall of the stripe; 10) removing the dielectric film from the polysilicon layer to expose an emitter contact on an upper surface of the stripe.

Claim 2

A method for forming a vertical heterojunction bipolar transistor having a lateral connector contact, comprising: 1) providing a silicon on insulator (SOI) substrate; 2) placing an epitaxial layer on the substrate, the epitaxial layer comprising a collector layer, a base layer above the collector layer and an emitter layer above the base layer; 3) etching away all but a portion of the epitaxial layer and of the silicon layer of the SOI substrate down to the oxide layer of the SOI substrate, the portion of the epitaxial layer constituting a device region; 4) forming a first dielectric sidewall spacer adjacent the device region and the portion of the silicon layer; 5) depositing a polysilicon layer having a dielectric film thereon on the device region, the first dielectric sidewall spacer and the SOI substrate, and etching the dielectric film and the polysilicon layer to leave a stripe of the polysilicon with dielectric on top, the stripe overhanging at least two edges of the device region; 6) etching away an exposed portion of the device region to expose a portion of an upper surface of the silicon layer of the SOI substrate, and doping the exposed upper surface to form a collector contact link; 7) forming a second dielectric sidewall spacer adjacent the stripe, the second dielectric sidewall spacer abutting the device region and the polysilicon layer on one side of the stripe, the second dielectric sidewall spacer abutting the polysilicon layer on an opposite side of the stripe; 8) forming a collector contact on the silicon of the SOI substrate adjacent the one wall of the stripe; 9) forming a base contact on the device region adjacent the opposite wall of the stripe; 10) removing the dielectric film from the polysilicon layer to expose an emitter contact on an upper surface of the stripe.