Bipolar transistor structure with self-aligned device and isolation and fabrication process therefor

Claim 1

A method for fabricating a bipolar device structure having device and isolation regions fully self-aligned comprising the steps of: on a substrate of first conductivity type semiconductor material, the step of forming a first layer composed of epitaxial semiconductor material to provide a device collector layer, forming a second layer composed of second conductivity type semiconductor material on said first layer to provide a device base layer, forming a third layer composed of first conductivity type semiconductor material on said second layer to provide a device emitter layer, forming a fourth layer composed of a first type of electrical insulating material on said third layer, forming a fifth layer composed of a second type of electrical insulating material on said fourth layer, forming a sixth layer composed of photoresistive material on said fifth layer, masking, exposing and developing said sixth layer of photoresistive material to form patterned openings in said sixth layer for defining transistor device areas on said fifth layer, using said patterned sixth layer of photoresistive material as an etch mask, etching away corresponding portions of said fourth and fifth layers of insulating material to form trench regions, filling said trench regions with metal and metal silicide material, masking and etching the metal and metal silicide material from selected ones of said trench regions, leaving said metal and metal silicide in an unselected trench region intermediate said selected trench regions from which said metal and metal silicide has been etched away, said unselected trench region being a device emitter region, further etching said selected trench regions through said first, second and third layers and into a portion of said substrate, filling said selected, etched trench regions with electrical insulating material for forming device isolation regions which are self-aligned with said device emitter region, and forming extrinsic base and collector regions between said isolation regions and said emitter region.

Claim 2

A method for fabricating a bipolar device structure having device and isolation regions fully self-aligned comprising the steps of: on a substrate of first conductivity type semiconductor material, the step of forming a first layer composed of epitaxial semiconductor material to provide a device collector layer, forming a second layer composed of second conductivity type semiconductor material on said first layer to provide a device base layer, forming a third layer composed of first conductivity type semiconductor material on said second layer to provide a device emitter layer, forming a fourth layer composed of a first type of electrical insulating material on said third layer, forming a fifth layer composed of a second type of electrical insulating material on said fourth layer, forming a sixth layer composed of photoresistive material on said fifth layer, masking, exposing and developing said sixth layer of photoresistive material to form patterned openings in said sixth layer for defining transistor device areas on said fifth layer, using said patterned sixth layer of photoresistive material as an etch mask, etching away corresponding portions of said fourth and fifth layers of insulating material to form trench regions, filling said trench regions with metal and metal silicide material, masking and etching the metal and metal silicide material from selected ones of said trench regions, leaving said metal and metal silicide in an unselected trench region intermediate said selected trench regions from which said metal and metal silicide has been etched away, said unselected trench region being a device emitter region, further etching said selected trench regions through said first, second and third layers and into a portion of said substrate, filling said selected, etched trench regions with electrical insulating material for forming device isolation regions which are self-aligned with said device emitter region, and forming extrinsic base and collector regions between said isolation regions and said emitter region.