US5946559A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Membrane dielectric isolation IC fabrication
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 1995-06-07
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Granted: 1999-08-31
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Expires: 2015-06-07
Abstract
Abstract General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.
Inventors
- 👤 Glenn Joseph Leedy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 05:58
CPC Classifications
H; H10; H10W; H10W90/00; H10P; H10P95/00; G; G03; G03F; G03F7/00; G03F7/70; G03F7/70483; G03F7/70605; G03F7/70653; G03F7/70658; G11; G11C; G11C29/00; G11C29/006; H10P90/00; H10P90/19; H10P90/1904; H10P90/1906; H10W10/00; H10W10/01; H10W10/011; H10W10/021; H10W10/061; H10W10/10; H10W10/181; H10W10/20; H10W70/00; H10W70/60; H10W70/611; H10W70/62; H10W70/65; H10W70/67; H10W70/68; H10W70/685; H10W70/688; G02; G02F; G02F1/00; G02F1/01; G02F1/13; G02F1/133; G02F1/1333; G02F1/1345; G02F1/13452; G02F1/136; G02F1/1362; G02F1/136277; G02F1/136281; H10D; H10D84/00; H10D84/01; H10D84/02; H10D84/03; H10D84/038; H10D88/00; H10D88/01; H10D89/00; H10D89/10; H10W70/682; H10W72/00; H10W72/20; H10W72/221; H10W72/29; H10W72/90; H10W72/941; H10W72/942; H10W90/701; H10W90/721; H10W90/724; Y; Y10; Y10S; Y10S148/00; Y10S148/135; Y10S438/00; Y10S438/928; Y10S438/938; Y10S438/942; Y10S438/967; Y10S438/977; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49124; Y10T29/49128; Y10T29/49155; Y10T29/49162; Y10T29/49165; Y10T29/49169; Y10T29/49171; Y10T29/49204; Y10T29/49208; Y10T29/4921
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
178 words
A method of forming a field effect transistor having a narrow gate and opposed gate contact, comprising the steps of: forming a silicon layer less than about 10 μm thick; forming a gate electrode over the principal surface of the silicon layer; forming a low stress dielectric layer less than about 10 μm thick over the silicon layer and over the gate electrode; forming doped regions in the silicon layer; etching a groove in the silicon layer from the surface opposing the principal surface thereof in a portion of the silicon layer underlying the gate electrode; depositing metal in the groove to a predetermined depth; etching away the opposing surface of the silicon layer to the predetermined depth; depositing a mask layer on the etched-away surface; patterning the mask layer, thereby exposing portions of the etched-away surface; forming additional doped regions in the silicon layer at the exposed portions of the etched-away surface; removing the mask layer; and etching away additional portions the etched-away surface to the bottom of the groove, thereby removing all of the deposited metal.
Claim 2
Independent Claim
178 words
A method of forming a field effect transistor having a narrow gate and opposed gate contact, comprising the steps of: forming a silicon layer less than about 10 μm thick; forming a gate electrode over the principal surface of the silicon layer; forming a low stress dielectric layer less than about 10 μm thick over the silicon layer and over the gate electrode; forming doped regions in the silicon layer; etching a groove in the silicon layer from the surface opposing the principal surface thereof in a portion of the silicon layer underlying the gate electrode; depositing metal in the groove to a predetermined depth; etching away the opposing surface of the silicon layer to the predetermined depth; depositing a mask layer on the etched-away surface; patterning the mask layer, thereby exposing portions of the etched-away surface; forming additional doped regions in the silicon layer at the exposed portions of the etched-away surface; removing the mask layer; and etching away additional portions the etched-away surface to the bottom of the groove, thereby removing all of the deposited metal.
Claim 3
Dependent Claim
24 words
The method of claim 1, further comprising the steps of forming a trench in the silicon layer surrounding the active portion of the transistor.
Claim 4
Independent Claim
93 words
A method of forming a transistor, comprising the steps of: providing a flexible membrane having a thin film of semiconductor material formed on the membrane; forming a trench in the semiconductor material; doping portions of the semiconductor material; laterally growing extensions of the sidewalls of the trench, thereby narrowing the trench to a predetermined width; filling the remaining width of the trench with semiconductor material doped at a concentration differing from a doping level of the extensions; and forming an electrical contact to the filled portion of the trench through the flexible membrane.
Claim 5
Independent Claim
93 words
A method of forming a transistor, comprising the steps of: providing a flexible membrane having a thin film of semiconductor material formed on the membrane; forming a trench in the semiconductor material; doping portions of the semiconductor material; laterally growing extensions of the sidewalls of the trench, thereby narrowing the trench to a predetermined width; filling the remaining width of the trench with semiconductor material doped at a concentration differing from a doping level of the extensions; and forming an electrical contact to the filled portion of the trench through the flexible membrane.
Claim 6
Dependent Claim
25 words
The method of claim 3, further comprising the step of isolating the trench by forming additional trenches in the semiconductor material surrounding the first trench.
Claim 7
Dependent Claim
64 words
The method of claim 3, further comprising the steps, prior to the step of laterally growing, of: forming a mask layer over a principal surface of the thin film of semiconductor material; etching away sidewalls of the trench, thereby forming a cavity under the mask layer; and laterally growing a plurality of differently doped layers of semiconductor material on the sidewalls of the cavity.
Claim 8
Dependent Claim
85 words
A field effect transistor comprising: a flexible dielectric membrane having a principal surface; a semiconductor film formed on the principal surface of the membrane, the semiconductor film including at least three doped layers; a contact to a first of the three doped layers formed through the membrane; a contact to a second of the doped layers formed on a principal surface of the semiconductor film; an insulating layer formed over an edge of the semiconductor film; and a gate electrode formed overlying the insulating layer.
Claim 9
Dependent Claim
85 words
A field effect transistor comprising: a flexible dielectric membrane having a principal surface; a semiconductor film formed on the principal surface of the membrane, the semiconductor film including at least three doped layers; a contact to a first of the three doped layers formed through the membrane; a contact to a second of the doped layers formed on a principal surface of the semiconductor film; an insulating layer formed over an edge of the semiconductor film; and a gate electrode formed overlying the insulating layer.
Claim 10
Dependent Claim
21 words
The device of claim 6, wherein a portion of the third layer extends over edges of the first and second layers.
Claim 11
Dependent Claim
50 words
The device of claim 6 wherein the third layer is located intermediate of the first and second layers, and a portion of the third layer extends over edges of the first and second layers, and wherein the contact to the third layer overlies the extended portion of the third layer.
Claim 12
Independent Claim
124 words
A method of forming a field effect transistor comprising the steps of: providing a membrane comprising a semiconductor layer overlying a low stress dielectric layer; forming a drain region and a source region laterally spaced apart from the drain region in the semiconductor layer, a portion of the semiconductor layer between the source and drain regions being a gate region; forming an insulating layer overlying the semiconductor layer; and forming a gate electrode on the insulating layer, one edge of the gate electrode being in a plane defined by an interface of one of the source region or the drain region and the gate region, and a second edge of the gate electrode extending over the other of the drain region or source region.
Claim 13
Independent Claim
124 words
A method of forming a field effect transistor comprising the steps of: providing a membrane comprising a semiconductor layer overlying a low stress dielectric layer; forming a drain region and a source region laterally spaced apart from the drain region in the semiconductor layer, a portion of the semiconductor layer between the source and drain regions being a gate region; forming an insulating layer overlying the semiconductor layer; and forming a gate electrode on the insulating layer, one edge of the gate electrode being in a plane defined by an interface of one of the source region or the drain region and the gate region, and a second edge of the gate electrode extending over the other of the drain region or source region.
Claim 14
Independent Claim
96 words
A method of forming a transistor comprising the steps of: providing a flexible membrane including a low stress dielectric layer and a semiconductor layer; forming a first and a second doped regions in the semiconductor layer, the first and second doped regions being vertically spaced apart and separated by a control region; epitaxially growing an extension of the control region extending over an edge of the semiconductor layer and contacting edges of the first and second doped regions; and forming electrical contacts to the first and second doped regions and to extension of the control region.
Claim 15
Independent Claim
96 words
A method of forming a transistor comprising the steps of: providing a flexible membrane including a low stress dielectric layer and a semiconductor layer; forming a first and a second doped regions in the semiconductor layer, the first and second doped regions being vertically spaced apart and separated by a control region; epitaxially growing an extension of the control region extending over an edge of the semiconductor layer and contacting edges of the first and second doped regions; and forming electrical contacts to the first and second doped regions and to extension of the control region.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-08-30 | 2003-03-01 | 2003-08-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-08-30 | 2007-03-01 | 2007-08-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-08-30 | 2011-03-01 | 2011-08-31 | $7700.00 | Window Closed / Lapsed |