US4070230A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor component with dielectric carrier and its manufacture
Assignee: Siemens AG
•
Filing: 1976-06-04
•
Granted: 1978-01-24
•
Expires: 1996-06-04
Abstract
Abstract A semiconductor component of a semiconductor or circuit system is provided. The circuit incorporates a dielectric carrier comprised of synthetic material. The circuit is provided with plate-shaped semiconductor islands. The islands possess doping layers and are interconnected as desired with a thin film wiring. A process for the production of such product is also provided.
Inventors
- 👤 Karl-Ulrich Stein
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 03:35
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/60; H10P14/63; H10P14/6326; H10P14/6342; H10D; H10D86/00; H10D86/01; H10P14/65; H10P14/6516; H10P14/6536; H10P14/6538; H10P14/68; H10P14/683; H10W; H10W10/00; H10W10/01; H10W10/021; H10W10/20; H10W20/00; H10W20/01; H10W20/40; H10W74/00; H10W74/10; H10W74/131; H10W74/137; Y; Y10; Y10S; Y10S438/00; Y10S438/977
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
147 words
A process for the production of a component assembly incorporating a flattened, integrated semiconductor circuit of the type having a plurality of discrete sites of doped, semiconductor material which discrete sites are interconnected together in a predetermined manner by layered paths of conductive material, said process comprising the steps of: A. forming a said semiconductor circuit on an n + conducting silicon wafer by depositing an n - conductive monocrystalline epitaxial silicon layer thereon, diffusing p-conducting doping material into said epitaxial layer selectively to form doped zones, depositing an insulative layer selectively thereover, and depositing electrically conductive paths selectively thereover, B. forming a layer of polyamide resin over the resulting said semiconductor circuit, C. heating said layer of polyamide resin to convert same into a layer of polyimide resin, D. selectively etching away portions of said n + silicon wafer and said n - epitaxial silicon layer.
Claim 2
Dependent Claim
147 words
A process for the production of a component assembly incorporating a flattened, integrated semiconductor circuit of the type having a plurality of discrete sites of doped, semiconductor material which discrete sites are interconnected together in a predetermined manner by layered paths of conductive material, said process comprising the steps of: A. forming a said semiconductor circuit on an n + conducting silicon wafer by depositing an n - conductive monocrystalline epitaxial silicon layer thereon, diffusing p-conducting doping material into said epitaxial layer selectively to form doped zones, depositing an insulative layer selectively thereover, and depositing electrically conductive paths selectively thereover, B. forming a layer of polyamide resin over the resulting said semiconductor circuit, C. heating said layer of polyamide resin to convert same into a layer of polyimide resin, D. selectively etching away portions of said n + silicon wafer and said n - epitaxial silicon layer.
Claim 3
Dependent Claim
22 words
The process of claim 1 wherein, following said etching away, only plate-shaped doped islands of said n - epitaxial silicon layer remain.
Claim 4
Dependent Claim
19 words
The process of claim 1 wherein said polyamide resin layer is applied in the form of a photo-lacquer layer.
Claim 5
Dependent Claim
56 words
The process of claim 1 wherein said portions of said n + silicon wafer so selectively etched away lie over said resulting semiconductor circuit whereby a frame of said n + silicon wafer remains perimetrically about peripheral edge portions of said resulting semiconductor circuit, said frame serving as a support for said layer of polyamide resin.
Claim 6
Dependent Claim
22 words
The process of claim 4 wherein soldering bumps are applied through said layer of polyamide resin over the region of said frame.
Claim 7
Dependent Claim
65 words
The process of claim 5 wherein a plurality of said circuits are simultaneously so produced by said steps, said plurality being arranged in spaced, parallel laterally adjacent rows upon said silicon wafer, said frame of each said resulting semiconductor circuit being interconnected to each laterally adjacent said resulting semiconductor circuit by thin arms comprised of said silicon wafer, said arms being adapted for transverse slitting.
Claim 8
Dependent Claim
17 words
The process of claim 6 wherein following said etching, the resulting surface is passivated by ion implantation.
Claim 9
Dependent Claim
22 words
The process of claim 6 wherein following said etching the resulting surface is passivated by coating with a layer of synthetic resin.
References Cited (Backward Citations)
US3616345A
Cited
US4001870A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-01-23 | 1981-07-25 | 1982-01-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-01-23 | 1985-07-25 | 1986-01-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-01-23 | 1989-07-25 | 1990-01-24 | $7700.00 | Window Closed / Lapsed |