Use of SiD4 for deposition of ultra thin and controllable oxides

Abstract

Abstract This invention includes a novel synthesis of a three-step process of growing, depositing and growing SiO 2 under low pressure, e.g., 0.2-10 Torr, to generate high quality, robust and reliable gate oxides for sub 0.5 micron technologies. The first layer, 1.0-3.0 nm is thermally grown for passivation of the Si-semiconductor surface. The second deposited layer, which contains a substantial concentration of a hydrogen isotope, such as deuterium, forms an interface with the first grown layer. During the third step of the synthesis densification of the deposited oxide layers occurs with a simultaneous removal of the interface traps at the interface and growth of a stress-modulated SiO 2 occurs at the Si/first grown layer interface in the presence of a stress-accommodating interface layer resulting in a planar and stress-reduced Si/SiO 2 interface. The entire synthesis is done under low-pressure (e.g., 0.2-10 Torr) for slowing down the oxidation kinetics to achieve ultrathin sublayers and may be done in a single low-pressure furnace by clustering all three steps. For light nitrogen-incorporation (<5%) for certain devices, often required due to improved resistance to boron and other dopant diffusion and hot-carrier characteristics, N 2 O or NO in the oxidant are used during each steps of the stacked oxide synthesis. Planar and stress-reduced Si/SiO 2 interface characteristics is a unique signature of stacked oxide that improves robustness of the gate oxide to ULSI processing resulting in reduced scatter in device parameters (e.g., threshold voltage, transconductance) , mobility degradation, and resistance to hot-carrier and Fowler-Nordheim stress.

Inventors

• 👤 David C. Brady
• 👤 Isik C. Kizilyalli
• 👤 Yi Ma
• 👤 Pradip K. Roy

Bibliographic Details