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US4851370A Expired / Lapsed US ⏱️ 0.0 years remaining

Fabricating a semiconductor device with low defect density oxide

Assignee: Nokia Bell Labs
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Filing: 1987-12-28
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Granted: 1989-07-25
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Expires: 2007-12-28
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Abstract

Abstract Low defect density oxides suitable for use as thin gate oxides or in charge storage capacitors are described. First and second layers are formed on a substrate with misaligned defect structures. A third layer is then grown by diffusing a species through the first and second layers to the substrate. The species reacts with the substrate. The low defect density results from the misaligned defect structure of the first and second layers. In one embodiment, the first and second layers are grown and deposited oxides, respectively. The third layer is grown by diffusing oxygen through the first two layers and the interface between the first and second layers acts as a sink trapping defects. The oxide silicon interface has desirable characteristics because the oxide grows in near equilibrium conditions.

Inventors

  • 👤 Raymond H. Doklan
  • 👤 Edward P. Martin, Jr.
  • 👤 Pradip K. Roy
  • 👤 Scott F. Shive
  • 👤 Ashok K. Sinha

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 12:26
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01332; H10D64/01336; H10D64/0134; H10D64/60; H10D64/66; H10D64/68; H10D64/693; H10D64/01342; H10D64/01344; H10D64/01346; H10D64/01352; H10D64/681; H10D64/685; H10P; H10P14/00; H10P14/60; H10P14/65; H10P14/6516; H10P14/6518; H10P14/6519; H10P14/6522; H10P14/6529; H10P14/69; H10P14/692; H10P14/6921; H10P14/6922; H10P14/6927; H10P14/694; H10P14/6943; H10P14/69433; H10P14/63; H10P14/6302; H10P14/6304; H10P14/6306; H10P14/6308; H10P14/6309; H10P14/6322; H10P14/6326; H10P14/6328; H10P14/6334; H10P14/66; H10P14/662; H10P14/69215

Claims Analysis

Total Claims: 10
Claim 1
Independent Claim 143 words
A method of fabricating an integrated circuit comprising a thin, planar, oxide layer grown on a substrate, with an essentially stress-free interface formed therebetween, the method comprising the steps of: (a) growing a first oxide layer on an exposed surface portion of the substrate, said first oxide layer including defect structures; (b) forming a dielectric layer over said first oxide layer, said dielectric layer being of a composition which is transparent to an oxidizing species, said dielectric layer including defect structures, wherein the dual layer combination of said first oxide layer and said dielectric layer includes an interface defined therebetween; and (c) growing a second oxide layer underneath said first oxide layer by diffusing an oxidizing species through said dielectric and first oxide layers, said second oxide layer being a relatively thin layer which creates an essentially planar, stress-free interface with said substrate.
Claim 2
Independent Claim 143 words
A method of fabricating an integrated circuit comprising a thin, planar, oxide layer grown on a substrate, with an essentially stress-free interface formed therebetween, the method comprising the steps of: (a) growing a first oxide layer on an exposed surface portion of the substrate, said first oxide layer including defect structures; (b) forming a dielectric layer over said first oxide layer, said dielectric layer being of a composition which is transparent to an oxidizing species, said dielectric layer including defect structures, wherein the dual layer combination of said first oxide layer and said dielectric layer includes an interface defined therebetween; and (c) growing a second oxide layer underneath said first oxide layer by diffusing an oxidizing species through said dielectric and first oxide layers, said second oxide layer being a relatively thin layer which creates an essentially planar, stress-free interface with said substrate.
Claim 3
Dependent Claim 40 words
The method as defined in claim 1 wherein in performing step (b) the dielectric layer is formed such that the defect structures of said dielectric layer are misaligned with the defect structures of the first oxide grown in step (a).
Claim 4
Independent Claim 21 words
The method as defined in claims 1 or 2 wherein the dielectric layer of step (b) comprises a deposited oxide layer.
Claim 5
Dependent Claim 26 words
The method as defined in claim 3 wherein in performing step (b) the oxide is formed by low pressure chemical vapor deposition decomposition of tetraethoxysilane (TEOS).
Claim 6
Dependent Claim 37 words
The method as defined in claim 4 wherein in performing the deposition of step b), the deposition temperature is in the range of approximately 625°-750° C. and the deposition pressure is between approximately 150 and 400 mtorr.
Claim 7
Independent Claim 31 words
The method as defined in claims 1 or 2 wherein in performing step (b), the dielectric layer comprises a deposited silicon nitride layer which is completely oxidized to form silicon oxynitride.
Claim 8
Independent Claim 26 words
The method as defined in claims 1 or 2 wherein in performing step (b), the dielectric layer comprises a deposited polysilicon layer which is subsequently oxidized.
Claim 9
Dependent Claim 111 words
The method as defined in claim 1 wherein in performing step (c), the following steps are performed: (c 1 ) exposing the substrate to an ambient temperature of approximately 750° C.; (c 2 ) increasing the ambient temperature to within the range of approximately 850°-900° C.; (c 3 ) introducing a gas including the oxidizing species into the atmosphere surrounding the substrate; (c 4 ) maintaining the substrate in the oxygen atmosphere for a predetermined period of time related to the desired thickness of the second oxide layer; (c 5 ) removing the oxygen atmosphere and decreasing the ambient temperature to approximately 750° C.; and (c 6 ) cooling the substrate.
Claim 10
Dependent Claim 27 words
The method as defined in claim 8 wherein in performing step (c 3 ), the gas flow comprises an oxygen content in the range of approximately 20-55%.

References Cited (Backward Citations)

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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1992-07-24 1993-01-23 1993-07-25 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1996-07-24 1997-01-23 1997-07-25 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2000-07-24 2001-01-23 2001-07-25 $7700.00 Window Closed / Lapsed

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