US6090684A
Expired / Lapsed
US
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Method for manufacturing semiconductor device
Assignee: Hitachi Ltd
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Filing: 1999-07-29
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Granted: 2000-07-18
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Expires: 2019-07-29
Abstract
Abstract A shallow groove isolation structure (SGI) electrically insulates adjoining transistors on a semiconductor substrate. A pad oxide film is formed on the semiconductor substrate and an oxidation inhibition film is formed on the pad oxide film. Parts of the oxide inhibition film and pad oxide film are removed to form the groove. In particular, the pad oxide film is removed from an upper edge of the groove within a range of 5 to 40 nm. A region of the groove is oxidized in an oxidation environment with a cast ratio of hydrogen (H 2 ) to oxygen (O 2 ) being less than or equal to 0.5. At this ratio, the oxidizing progresses under low stress at the upper groove edges of the substrate thereby enabling rounding of the upper groove edges without creating a level difference at or near the upper groove edge on the substrate surface.
Inventors
- 👤 Norio Ishitsuka
- 👤 Hideo Miura
- 👤 Shuji Ikeda
- 👤 Yasuko Yoshida
- 👤 Norio Suzuki
- 👤 Masayuki Kojima
- 👤 Kota Funayama
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 12:43
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/014; H10W10/0145; H10W10/10; H10W10/17; Y; Y10; Y10S; Y10S148/00; Y10S148/05
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
156 words
In a method for manufacturing a semiconductor device which has a shallow groove isolation structure: (a) providing a semiconductor substrate; (b) forming a pad oxide film above a circuit formation surface of said semiconductor substrate; (c) forming an oxide inhibition film above said pad oxide film; (d) after said forming of the oxide inhibition film, removing parts of said oxide inhibition film, said pad oxide film and forming a groove in said semiconductor substrate; (e) removing said pad oxide film from an upper edge of said groove within a range of from 5 to 40 nm; (f) after said removing said pad oxide film step, oxidizing a region of said groove; and between said removing said pad oxide film step and before said oxidizing a region of said groove step, isotropically etching exposed surface portions of said semiconductor substrate of equal to or less than 20 nm in depth from a surface of said semiconductor substrate.
Claim 2
Dependent Claim
156 words
In a method for manufacturing a semiconductor device which has a shallow groove isolation structure: (a) providing a semiconductor substrate; (b) forming a pad oxide film above a circuit formation surface of said semiconductor substrate; (c) forming an oxide inhibition film above said pad oxide film; (d) after said forming of the oxide inhibition film, removing parts of said oxide inhibition film, said pad oxide film and forming a groove in said semiconductor substrate; (e) removing said pad oxide film from an upper edge of said groove within a range of from 5 to 40 nm; (f) after said removing said pad oxide film step, oxidizing a region of said groove; and between said removing said pad oxide film step and before said oxidizing a region of said groove step, isotropically etching exposed surface portions of said semiconductor substrate of equal to or less than 20 nm in depth from a surface of said semiconductor substrate.
Claim 3
Dependent Claim
155 words
In a method for manufacturing a semiconductor device which has a shallow groove isolation structure, comprising the steps of: (a) providing a semiconductor substrate that has a pad oxide film and an oxide inhibition film laminated on a circuit formation surface of said semiconductor substrate, and further has parts of said oxide inhibition film and said pad oxide film removed, and a groove formed in said circuit formation surface of said semiconductor substrate; (b) removing said pad oxide film from an upper edge of said groove within a range of from 5 to 40 nm; (c) after said removing said pad oxide film step, oxidizing a region of said groove; and between said removing said pad oxide film step and before said oxidizing a region of said groove step, isotropically etching exposed surface portions of said semiconductor substrate of equal to or less than 20 nm in depth from a surface of said semiconductor substrate.
Claim 4
Dependent Claim
155 words
In a method for manufacturing a semiconductor device which has a shallow groove isolation structure, comprising the steps of: (a) providing a semiconductor substrate that has a pad oxide film and an oxide inhibition film laminated on a circuit formation surface of said semiconductor substrate, and further has parts of said oxide inhibition film and said pad oxide film removed, and a groove formed in said circuit formation surface of said semiconductor substrate; (b) removing said pad oxide film from an upper edge of said groove within a range of from 5 to 40 nm; (c) after said removing said pad oxide film step, oxidizing a region of said groove; and between said removing said pad oxide film step and before said oxidizing a region of said groove step, isotropically etching exposed surface portions of said semiconductor substrate of equal to or less than 20 nm in depth from a surface of said semiconductor substrate.
Claim 5
Dependent Claim
205 words
In a method for manufacturing a semiconductor device: (a) forming a pad oxide film on a circuit formation surface of a semiconductor substrate; (b) forming an oxide inhibition film on said pad oxide film; (c) removing portions of said oxide inhibition film and said pad oxide film at desired positions to expose corresponding surface portions of said semiconductor substrate; (d) forming a groove of specified depth in said semiconductor substrate with said oxide inhibition film used as a mask; (e) removing said pad oxide film from an upper edge of said groove within a range of from 5 to 40 nm; (f) isotropically etching for removal resultant exposed surface portions of said semiconductor substrate within 20 nm; (g) oxidizing a groove portion as formed in said semiconductor substrate; (h) burying a dielectric film within the groove thus oxidized; (i) removing a portion or portions of the buried dielectric film as formed on said oxide inhibition film; (j) removing more than one portion of said oxide inhibition film as formed on or over the circuit formation surface of said semiconductor substrate; and (k) removing more than one portion of said pad oxide film being formed on or over the circuit formation surface of said semiconductor substrate.
Claim 6
Dependent Claim
205 words
In a method for manufacturing a semiconductor device: (a) forming a pad oxide film on a circuit formation surface of a semiconductor substrate; (b) forming an oxide inhibition film on said pad oxide film; (c) removing portions of said oxide inhibition film and said pad oxide film at desired positions to expose corresponding surface portions of said semiconductor substrate; (d) forming a groove of specified depth in said semiconductor substrate with said oxide inhibition film used as a mask; (e) removing said pad oxide film from an upper edge of said groove within a range of from 5 to 40 nm; (f) isotropically etching for removal resultant exposed surface portions of said semiconductor substrate within 20 nm; (g) oxidizing a groove portion as formed in said semiconductor substrate; (h) burying a dielectric film within the groove thus oxidized; (i) removing a portion or portions of the buried dielectric film as formed on said oxide inhibition film; (j) removing more than one portion of said oxide inhibition film as formed on or over the circuit formation surface of said semiconductor substrate; and (k) removing more than one portion of said pad oxide film being formed on or over the circuit formation surface of said semiconductor substrate.
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USPTO Annuity & Maintenance Windows
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| 3.5 Years (Year 4) | 2003-07-18 | 2004-01-17 | 2004-07-18 | $2000.00 | Window Closed / Lapsed |
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