US4952524A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device manufacture including trench formation
Assignee: Agere Systems LLC
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Filing: 1989-05-05
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Granted: 1990-08-28
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Expires: 2009-05-05
Abstract
Abstract A trench which provides electrical isolation between transistors on an integrated circuit substrate is described. The trench is lined with a diffusion barrier, typically a thermal oxide followed by a thermal stress relief layer, typically formed from TEOS. Then a filler material, typically BPTEOS, is deposited to fill the trench and cover the upper surface of the wafer. The filler material is heated to make it flow. Next the outer surface of the flowed filler material is next subjected to an etch-back which makes the top surface of the filled trench protrude slightly above the upper surface of the substrate. The resulting trench contains the diffusion barrier layer, the thermal stress relief layer, and the filler material. The filler material and the thermal stress relief layer will soften during subsequent heat treatments of the wafer, thus relieving thermal stresses, and preventing the occurrence of defects and dislocations within the wafer.
Inventors
- 👤 Kuo-Hua Lee
- 👤 Chih-Yuan Lu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 00:05
CPC Classifications
H; H10; H10P; H10P95/00; H10P95/06; H10P95/062; H10P95/064; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/014; H10W10/0143; H10W10/10; H10W10/17; H10P14/00; H10P14/60; H10P14/63; H10P14/6326; H10P14/6328; H10P14/6334; H10P14/66; H10P14/668; H10P14/6681; H10P14/6684; H10P14/6686; H10P14/69; H10P14/692; H10P14/6921; H10P14/69215; H10P14/6922; H10P14/6923; H10P14/694; H10P14/6943; H10P14/69433
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
101 words
A method of semiconductor device fabrication comprising: forming a trench into a substrate; forming a diffusion barrier layer in said trench; characterized by the further steps of depositing a thermal stress-relief layer upon said barrier layer; depositing a filler material upon said thermal stress relief layer, said filler material having an outer surface and filling said trench, said filler material having a flow temperature which is lower than the flow temperature of said thermal stress relief layer; heating said filler material to at least its flow temperature to smooth said outer surface; and etching back said upper surface of filler material.
Claim 2
Independent Claim
101 words
A method of semiconductor device fabrication comprising: forming a trench into a substrate; forming a diffusion barrier layer in said trench; characterized by the further steps of depositing a thermal stress-relief layer upon said barrier layer; depositing a filler material upon said thermal stress relief layer, said filler material having an outer surface and filling said trench, said filler material having a flow temperature which is lower than the flow temperature of said thermal stress relief layer; heating said filler material to at least its flow temperature to smooth said outer surface; and etching back said upper surface of filler material.
Claim 3
Dependent Claim
10 words
The method of claim 1 wherein said substrate is silicon.
Claim 4
Dependent Claim
28 words
The method of claim 1 wherein said thermal stress relief layer is formed by deposition of a material chosen from the group consisting of tetraethoxysilane, diacetoxyditertiarybutoxysilane, and tetramethylcyclotetrasiloxane.
Claim 5
Dependent Claim
14 words
The method of claim 1 wherein said thermal stress relief layer is borophosphosilicate glass.
Claim 6
Dependent Claim
32 words
The method of claim 1 wherein said filler material is formed by deposition of a material chosen from the group consisting of: tetraethoxysilane, diacetoxyditertiarybutoxysilane, and tetramethylcyclotetrasiloxane, together with dopants to promote flowability.
Claim 7
Dependent Claim
12 words
The method of claim 1 wherein said diffusion barrier is silicon dioxide.
Claim 8
Dependent Claim
18 words
The method of claim 1 wherein said filler material contains 3±1/2 percent each boron and phosphorous by weight.
Claim 9
Dependent Claim
45 words
The method of claim 1 wherein said etching-back step includes the steps of: depositing a resist material upon said outer surface of said filler material; planarizing said resist; and, etching said resist and said filler material to expose the outer surface of said filler material.
Claim 10
Dependent Claim
18 words
The method of claim 1, wherein said heating step and said etching-back step are performed more than once.
Claim 11
Dependent Claim
18 words
The method of claim 1, wherein said heating step is performed in a furnace at 950° C.±50° C.
Claim 12
Dependent Claim
18 words
The method of claim 1, wherein said heating step is accomplished by rapid thermal annealing at 1050±50° C.
Claim 13
Dependent Claim
28 words
The method of claim 1 wherein said filler material contains dopants and wherein said thermal stress relief layer contains dopants in a lesser concentration than said filler material.
Claim 14
Independent Claim
271 words
A method for semiconductor device manufacture comprising: depositing a first silicon dioxide layer upon a surface of a silicon substrate; depositing a layer of silicon nitride upon said first layer of silicon dioxide; selectively etching through said silicon dioxide layer and said silicon nitride layer into said silicon substrate to form at least one trench, said trench having sidewalls and a bottom, a portion of said first silicon dioxide layer, and said silicon nitride layer remaining on said silicon surface; forming a second silicon dioxide layer on said sidewalls and said bottom of said trench; depositing a thermal stress relief layer upon said second silicon dioxide layer, said thermal stress relief layer being formed by the decomposition of an oxide precursor gas, said thermal stress relief layer defining a cavity within said trench; depositing a flowable filler material into said cavity, said filler material being produced by the decomposition of an oxide percursor gas, together with boron and phosphorous, said filler material being thick enough to substantially fill said cavity and to have a thickness above said surface of said silicon substrate, said flowable filler material having a flow temperature lower than the flow temperature of said thermal stress relief layer; heating said flowable filler material to cause said filler material to flow; etching back said filler material, together with said portion of said first silicon dioxide layer remaining on said silicon surface and together with the said portion of said silicon nitride layer remaining on said silicon surface to expose said silicon surface and to create an upper surface on said filler material which protrudes slightly above said silicon surface.
Claim 15
Independent Claim
271 words
A method for semiconductor device manufacture comprising: depositing a first silicon dioxide layer upon a surface of a silicon substrate; depositing a layer of silicon nitride upon said first layer of silicon dioxide; selectively etching through said silicon dioxide layer and said silicon nitride layer into said silicon substrate to form at least one trench, said trench having sidewalls and a bottom, a portion of said first silicon dioxide layer, and said silicon nitride layer remaining on said silicon surface; forming a second silicon dioxide layer on said sidewalls and said bottom of said trench; depositing a thermal stress relief layer upon said second silicon dioxide layer, said thermal stress relief layer being formed by the decomposition of an oxide precursor gas, said thermal stress relief layer defining a cavity within said trench; depositing a flowable filler material into said cavity, said filler material being produced by the decomposition of an oxide percursor gas, together with boron and phosphorous, said filler material being thick enough to substantially fill said cavity and to have a thickness above said surface of said silicon substrate, said flowable filler material having a flow temperature lower than the flow temperature of said thermal stress relief layer; heating said flowable filler material to cause said filler material to flow; etching back said filler material, together with said portion of said first silicon dioxide layer remaining on said silicon surface and together with the said portion of said silicon nitride layer remaining on said silicon surface to expose said silicon surface and to create an upper surface on said filler material which protrudes slightly above said silicon surface.
References Cited (Backward Citations)
JPS5712533A
Cited
CA1196428A
Cited
US4506435A
Cited
JPS58143548A
Cited
JPS5963739A
Cited
JPS59106133A
Cited
JPS6043843A
Cited
US4543706A
Cited
JPS618944A
Cited
JPS6190442A
Cited
US4571819A
Cited
EP0232748A1
Cited
JPS62216261A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-08-27 | 1994-02-26 | 1994-08-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-08-27 | 1998-02-26 | 1998-08-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-08-27 | 2002-02-26 | 2002-08-28 | $7700.00 | Window Closed / Lapsed |