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JPS5963739A Expired / Lapsed JP ⏱️ 0.0 years remaining

Method for insulation and isolation of semiconductor device

Assignee: Panasonic Holdings Corp
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Filing: 1982-10-04
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Granted: —
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Expires: 2002-10-04
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Abstract

Abstract PURPOSE:To perform element isolation without crystal defects by decreasing heat-fusion temperature and thus preventing the evaporation of phosphorus by a method wherein a layer of high comcentration of phosphorus is superposed on a layer of low one, after thermally oxidizing the wall surface of a groove for isolation on an Si substrate. CONSTITUTION:A resist mask 4 is applied by superposing an SiO2 and an Si3N4 on the P type Si substrate 1, and the groove 5 is formed by reactive sputtering. A boron implanted layer 16 formed at the bottom of the groove after treatment with the mixed solution of fluoric acid and nitric acid. It is covered with an SiO2 7, a PSG8 with phosphorus at 5-20mol%, a PSG9 with phosphorus at 0.5-2mol% are superposed, and then reactive ion etching is performed by applying a resist mask 10. When heating is performed with infrared rays for 10-60sec after removing the mask, the PSG fuses and fills 10 the groove 5. The PSG9 of the low concentration of phosphorus prevents the evaporation of phosphorus from the PSG8; accordingly a good insulation isolation layer of a smooth surface can be formed.

Inventors

  • 👤 Masahiro Kuwagata
  • 👤 桑形 正博

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-05 12:22
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/014; H10W10/10; H10W10/17

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