Material removal method for forming a structure

Claim 1

A method of selectively removing material from a semiconductor substrate comprising: providing a volume of a material on a semiconductor substrate, said volume of said material having a first portion and a second portion, the first portion having therein a lower stress than that of the second portion; and selectively removing the material from the second portion at a material removal rate that is greater than that of the first portion.

Claim 2

A method of selectively removing material from a semiconductor substrate comprising: providing a volume of a material on a semiconductor substrate, said volume of said material having a first portion and a second portion, the first portion having therein a lower stress than that of the second portion; and selectively removing the material from the second portion at a material removal rate that is greater than that of the first portion.

Claim 13

A method of selectively removing material from a semiconductor substrate comprising: forming a volume of a material upon on a semiconductor substrate, the volume of the material having uniform stress throughout; reducing the stress in a first portion of the volume of the material without reducing the stress in a second portion of the volume of the material; and selectively removing the material from the second portion at a material removal rate that is greater than that of the first portion.

Claim 14

A method of selectively removing material from a semiconductor substrate comprising: forming a volume of a material upon on a semiconductor substrate, the volume of the material having uniform stress throughout; reducing the stress in a first portion of the volume of the material without reducing the stress in a second portion of the volume of the material; and selectively removing the material from the second portion at a material removal rate that is greater than that of the first portion.

Claim 19

A method of selectively removing material from a semiconductor substrate comprising: providing a volume of a material located on a semiconductor substrate, said volume of said material having therein a first portion and a second portion, the first portion having implanted therein a concentration of atomic particles that is greater than a concentration of said atomic particles that are implanted in the second portion; and selectively removing, by etching with a basic etchant, said material from the second portion at a material removal rate that is greater than that of the first portion.

Claim 20

A method of selectively removing material from a semiconductor substrate comprising: providing a volume of a material located on a semiconductor substrate, said volume of said material having therein a first portion and a second portion, the first portion having implanted therein a concentration of atomic particles that is greater than a concentration of said atomic particles that are implanted in the second portion; and selectively removing, by etching with a basic etchant, said material from the second portion at a material removal rate that is greater than that of the first portion.

Claim 22

A method of selectively removing material from a semiconductor substrate comprising: providing a volume of a material located on a semiconductor substrate, said volume of said material having therein a first portion and a second portion, the first portion having implanted therein a concentration of ions that is greater than a concentration of said ions that are implanted in the second portion, wherein said implanted ions in said volume of said material are undiffused subsequent to implantation therein, and wherein the volume of the material is composed of a silicon-containing material selected from a group consisting of monocrystalline silicon, amorphous silicon, spherical grain polysilicon, hemispherical grain polysilicon, and polysilicon; and selectively removing, by etching with a basic etchant, said material from the second portion at a material removal rate that is greater than that of the first portion.

Claim 23

A method of selectively removing material from a semiconductor substrate comprising: providing a volume of a material located on a semiconductor substrate, said volume of said material having therein a first portion and a second portion, the first portion having implanted therein a concentration of ions that is greater than a concentration of said ions that are implanted in the second portion, wherein said implanted ions in said volume of said material are undiffused subsequent to implantation therein, and wherein the volume of the material is composed of a silicon-containing material selected from a group consisting of monocrystalline silicon, amorphous silicon, spherical grain polysilicon, hemispherical grain polysilicon, and polysilicon; and selectively removing, by etching with a basic etchant, said material from the second portion at a material removal rate that is greater than that of the first portion.

Claim 25

A method of selectively removing material from a semiconductor substrate comprising: implanting a plurality of atomic particles into a volume of a material located on a semiconductor substrate to form therein a first and a second portion, the first portion having implanted therein a concentration of said atomic particles that is greater than a concentration of said atomic particles that are implanted in the second portion; and selectively removing, by etching with a basic etchant, said material from the second portion at a material removal rate that is greater than that of the first portion.

Claim 26

A method of selectively removing material from a semiconductor substrate comprising: implanting a plurality of atomic particles into a volume of a material located on a semiconductor substrate to form therein a first and a second portion, the first portion having implanted therein a concentration of said atomic particles that is greater than a concentration of said atomic particles that are implanted in the second portion; and selectively removing, by etching with a basic etchant, said material from the second portion at a material removal rate that is greater than that of the first portion.

Claim 44

A method of removing material from a semiconductor substrate, comprising: implanting ions into a volume of a material selected from the group consisting of a silicon-containing material and a germanium-containing material, and located on a semiconductor substrate to form therein a first and a second portion, the first portion having a concentration of said ions implanted therein that is greater than a concentration of said ions implanted in the second portion; maintaining the semiconductor substrate in a selected temperature range after said implanting of ions; and etching the volume of the material with an basic etchant so as to remove the material from the second portion at a material removal rate that is greater than that of the first portion, wherein the implanted ions in the volume of the material are not diffused prior to etching the volume of the material.

Claim 45

A method of removing material from a semiconductor substrate, comprising: implanting ions into a volume of a material selected from the group consisting of a silicon-containing material and a germanium-containing material, and located on a semiconductor substrate to form therein a first and a second portion, the first portion having a concentration of said ions implanted therein that is greater than a concentration of said ions implanted in the second portion; maintaining the semiconductor substrate in a selected temperature range after said implanting of ions; and etching the volume of the material with an basic etchant so as to remove the material from the second portion at a material removal rate that is greater than that of the first portion, wherein the implanted ions in the volume of the material are not diffused prior to etching the volume of the material.

Claim 46

A method as recited in claims 39 , wherein the silicon-containing material is composed of material selected from a group consisting of monocrystalline silicon, amorphous silicon, spherical grain polysilicon, hemispherical grain polysilicon, and polysilicon.

Claim 54

A method as recited in claims 39 , wherein implanting said ions into said volume of said material located on said semiconductor substrate comprises a plurality of ion implantation steps, and wherein: a portion of said ions in at least one of said plurality of implantation steps are of a selected type which alters the electrical properties of the volume of the material; and a portion of said ions in at least one of said plurality of implantation steps are of a selected type which does not alter the electrical properties of the volume of the material.

Claim 55

A method as recited in claims 39 , further comprising, prior to implanting said ions into said volume of said material located on said semiconductor substrate, doping the volume of the material with a dopant material that alters the electrical properties of the volume of the material.

Claim 56

A method of selectively removing material from a semiconductor substrate, comprising: implanting ions into a volume of a material selected from the group consisting of a silicon-containing material and a germanium-containing material and located on a semiconductor substrate to form therein a first and a second portion, the first portion having a concentration of said ions that is greater than that of the second portion, wherein said ions are of a selected type which does not alter the electrical properties of the volume of the material; and selectively removing the material from the second portion by exposing the volume of the material to a solution containing a basic etchant selected from the group consisting of ammonia, tetraethylammonium hydroxide, tetrabutylphosphonium hydroxide, tetraphenylarsonium hydroxide, KOH, and NaOH, wherein the second portion is removed at a material removal rate that is at least about 20 times greater than that of the first portion.

Claim 57

A method of selectively removing material from a semiconductor substrate, comprising: implanting ions into a volume of a material selected from the group consisting of a silicon-containing material and a germanium-containing material and located on a semiconductor substrate to form therein a first and a second portion, the first portion having a concentration of said ions that is greater than that of the second portion, wherein said ions are of a selected type which does not alter the electrical properties of the volume of the material; and selectively removing the material from the second portion by exposing the volume of the material to a solution containing a basic etchant selected from the group consisting of ammonia, tetraethylammonium hydroxide, tetrabutylphosphonium hydroxide, tetraphenylarsonium hydroxide, KOH, and NaOH, wherein the second portion is removed at a material removal rate that is at least about 20 times greater than that of the first portion.

Claim 58

A method of removing material from a semiconductor substrate, comprising: provides a volume of a material selected from the group consisting of a silicon-containing material and a germanium-containing material, the volume of the material being located on a semiconductor substrate that is doped with a dopant material to a dopant concentration in a range from about 1×10 15 dopant atoms per cm 3 to about 1×10 19 dopant atoms per cm 3 , wherein the dopant material alters the electrical properties of the volume of the material; implanting ions into the volume of the material located on the semiconductor substrate to form therein a first and a second portion, the first portion having a concentration of said ions implanted therein in a range from about 1×10 15 ions per cm 3 to about 1×10 22 ions per cm 3 , and the second portion having a concentration of said ions implanted therein that is less than about 1×10 15 ions per cm 3 , wherein implanting said ions into said volume of the material located on said semiconductor substrate comprises a plurality of ion implantation steps, and wherein: a portion of said ions in at least one of said plurality of implantation steps are of a conductivity type which alters the electrical properties of the volume of the material; and a portion of said ions in at least one of said plurality of implantation steps are of a conductivity type which does not alter the electrical properties of the volume of the material; maintaining the semiconductor substrate in a selected temperature range after said implanting of ions; and etching the volume of the material with an basic etchant so as to remove the material from the second portion at a material removal rate that is at least about 20 times greater than that of the first portion, wherein the implanted ions in the volume of the material are not diffused prior to etching the volume of the material.

Claim 59

A method of removing material from a semiconductor substrate, comprising: provides a volume of a material selected from the group consisting of a silicon-containing material and a germanium-containing material, the volume of the material being located on a semiconductor substrate that is doped with a dopant material to a dopant concentration in a range from about 1×10 15 dopant atoms per cm 3 to about 1×10 19 dopant atoms per cm 3 , wherein the dopant material alters the electrical properties of the volume of the material; implanting ions into the volume of the material located on the semiconductor substrate to form therein a first and a second portion, the first portion having a concentration of said ions implanted therein in a range from about 1×10 15 ions per cm 3 to about 1×10 22 ions per cm 3 , and the second portion having a concentration of said ions implanted therein that is less than about 1×10 15 ions per cm 3 , wherein implanting said ions into said volume of the material located on said semiconductor substrate comprises a plurality of ion implantation steps, and wherein: a portion of said ions in at least one of said plurality of implantation steps are of a conductivity type which alters the electrical properties of the volume of the material; and a portion of said ions in at least one of said plurality of implantation steps are of a conductivity type which does not alter the electrical properties of the volume of the material; maintaining the semiconductor substrate in a selected temperature range after said implanting of ions; and etching the volume of the material with an basic etchant so as to remove the material from the second portion at a material removal rate that is at least about 20 times greater than that of the first portion, wherein the implanted ions in the volume of the material are not diffused prior to etching the volume of the material.

Claim 62

A method of selectively removing material from a semiconductor substrate comprising: forming a mask over a volume of a material located on a semiconductor substrate to form an unmasked and a masked portion thereof, wherein the masked portion of the volume of the material is masked by said mask, and the unmasked portion of the volume of the material is not masked by the mask; implanting a plurality of atomic particles into the unmasked portion of the volume of the material such that the unmasked portion of the volume of the material has implanted therein a concentration of said atomic particles that is greater than a concentration of said atomic particles that are implanted in the masked portion of the volume of the material; and removing the mask from the masked portion; and selectively removing said material from the masked portion by etching with a basic etchant at a material removal rate that is greater than that of the unmasked portion.

Claim 63

A method of selectively removing material from a semiconductor substrate comprising: forming a mask over a volume of a material located on a semiconductor substrate to form an unmasked and a masked portion thereof, wherein the masked portion of the volume of the material is masked by said mask, and the unmasked portion of the volume of the material is not masked by the mask; implanting a plurality of atomic particles into the unmasked portion of the volume of the material such that the unmasked portion of the volume of the material has implanted therein a concentration of said atomic particles that is greater than a concentration of said atomic particles that are implanted in the masked portion of the volume of the material; and removing the mask from the masked portion; and selectively removing said material from the masked portion by etching with a basic etchant at a material removal rate that is greater than that of the unmasked portion.

Claim 66

A method of selectively removing material from a semiconductor substrate, comprising: forming a mask over a volume of a material selected from the group consisting of a silicon-containing material and a germanium-containing material and located on a semiconductor substrate to form an unmasked and a masked portion thereof, wherein the masked portion of the volume of the material is masked by said mask, and the unmasked portion of the volume of the material is not masked by the mask; directionally implanting ions into the volume of the material such that said ions are implanted beneath said mask within said masked portion, and so as to form therein: an ion concentration range greater than about 1×10 18 ions per cm 3 in said unmasked portion; and a lower ion concentration said masked portion; removing the masking substrate that masks the masked portion; and implanting a plurality of ions into the unmasked portion of the volume of the material such that the unmasked portion of the volume of the material has implanted therein a concentration of said ions that is greater than a concentration of said ions that are implanted in the masked portion of the volume of the material; and removing the mask from the masked portion; and exposing the volume of the material to a basic etchant to selectively remove by etching the masked portion at a material removal rate that is greater than that of the unmasked portion.

Claim 67

A method of selectively removing material from a semiconductor substrate, comprising: forming a mask over a volume of a material selected from the group consisting of a silicon-containing material and a germanium-containing material and located on a semiconductor substrate to form an unmasked and a masked portion thereof, wherein the masked portion of the volume of the material is masked by said mask, and the unmasked portion of the volume of the material is not masked by the mask; directionally implanting ions into the volume of the material such that said ions are implanted beneath said mask within said masked portion, and so as to form therein: an ion concentration range greater than about 1×10 18 ions per cm 3 in said unmasked portion; and a lower ion concentration said masked portion; removing the masking substrate that masks the masked portion; and implanting a plurality of ions into the unmasked portion of the volume of the material such that the unmasked portion of the volume of the material has implanted therein a concentration of said ions that is greater than a concentration of said ions that are implanted in the masked portion of the volume of the material; and removing the mask from the masked portion; and exposing the volume of the material to a basic etchant to selectively remove by etching the masked portion at a material removal rate that is greater than that of the unmasked portion.

Claim 71

A method of forming an interconnect structure on a semiconductor substrate, comprising: forming a volume of an electrically conductive material selected from the group consisting of a silicon-containing material and a germanium-containing material and situated upon a plurality of raised structures, each said raised structure projecting from a charge conducting region, each said charge conducting region being situated between adjacent raised structures and within a semiconductor substrate; planarizing the volume of the electrically conductive material to form thereon a planar surface that is co-planar with at least on planar surface on the raised structures; implanting ions into said volume of said electrically conductive material to form therein a first and a second portion, the first portion having a concentration of said ions implanted therein that is greater than the concentration of said ions that are implanted in said second portion; and selectively removing said electrically conductive material from the second portion, by etching with a basic etchant, at a material removal rate that is greater than that of the first portion, wherein at least one interconnect structure is formed, each said interconnect structure being composed of said first portion of said volume of said electrically conductive material, and each said interconnect structure being located on one of said charge conducting regions within said semiconductor substrate.

Claim 72

A method of forming an interconnect structure on a semiconductor substrate, comprising: forming a volume of an electrically conductive material selected from the group consisting of a silicon-containing material and a germanium-containing material and situated upon a plurality of raised structures, each said raised structure projecting from a charge conducting region, each said charge conducting region being situated between adjacent raised structures and within a semiconductor substrate; planarizing the volume of the electrically conductive material to form thereon a planar surface that is co-planar with at least on planar surface on the raised structures; implanting ions into said volume of said electrically conductive material to form therein a first and a second portion, the first portion having a concentration of said ions implanted therein that is greater than the concentration of said ions that are implanted in said second portion; and selectively removing said electrically conductive material from the second portion, by etching with a basic etchant, at a material removal rate that is greater than that of the first portion, wherein at least one interconnect structure is formed, each said interconnect structure being composed of said first portion of said volume of said electrically conductive material, and each said interconnect structure being located on one of said charge conducting regions within said semiconductor substrate.

Claim 74

A method of forming a capacitor storage node on a semiconductor substrate, comprising: forming a volume of an electrically conductive material selected from the group consisting of a silicon-containing material and a germanium-containing material and located upon a plurality of insulated gate stacks situated upon a semiconductor substrate, wherein adjacent insulated gate stacks have a charge conducting region therebetween that is situated within the semiconductor substrate, said volume of said electrically conductive material also being formed upon said charge conducting regions; forming a mask upon said volume of said electrically conductive material: adjacent to and above each of said charge conducting regions; and above each said insulated gate stack, wherein a masked portion of the volume of the electrically conductive material is masked by said mask, and an unmasked portion of the volume of the electrically conductive material is not masked by said mask; forming an additional layer of said electrically conductive material over said mask; selectively removing, in an anisotropic etch with a basic etchant, said material from the additional layer of said electrically conductive material over said mask to form therefrom at least one spacer therefrom extending from said volume of said electrically conductive material adjacent to and in contact with said mask; implanting ions into the volume of the electrically conductive material and the additional layer of said electrically conductive material so as to form: an ion concentration in said unmasked portion; and an ion concentration in said masked portion that is lower in implanted ions than that of said unmasked portion; removing said mask upon said volume of said electrically conductive material; and selectively removing said material from the unmasked portion at a material removal rate that is greater than that of the unmasked portion to form from said first implanted portion a capacitor storage node having said at least one spacer extending therefrom.

Claim 75

A method of forming a capacitor storage node on a semiconductor substrate, comprising: forming a volume of an electrically conductive material selected from the group consisting of a silicon-containing material and a germanium-containing material and located upon a plurality of insulated gate stacks situated upon a semiconductor substrate, wherein adjacent insulated gate stacks have a charge conducting region therebetween that is situated within the semiconductor substrate, said volume of said electrically conductive material also being formed upon said charge conducting regions; forming a mask upon said volume of said electrically conductive material: adjacent to and above each of said charge conducting regions; and above each said insulated gate stack, wherein a masked portion of the volume of the electrically conductive material is masked by said mask, and an unmasked portion of the volume of the electrically conductive material is not masked by said mask; forming an additional layer of said electrically conductive material over said mask; selectively removing, in an anisotropic etch with a basic etchant, said material from the additional layer of said electrically conductive material over said mask to form therefrom at least one spacer therefrom extending from said volume of said electrically conductive material adjacent to and in contact with said mask; implanting ions into the volume of the electrically conductive material and the additional layer of said electrically conductive material so as to form: an ion concentration in said unmasked portion; and an ion concentration in said masked portion that is lower in implanted ions than that of said unmasked portion; removing said mask upon said volume of said electrically conductive material; and selectively removing said material from the unmasked portion at a material removal rate that is greater than that of the unmasked portion to form from said first implanted portion a capacitor storage node having said at least one spacer extending therefrom.

Claim 76

A method of forming an interconnect structure on a semiconductor substrate in a CMOS process flow, comprising: providing a semiconductor substrate having a PMOS portion thereon and an NMOS portion thereon, the PMOS portion and the NMOS portion each having a gate region formed therein; forming a PMOS mask over the PMOS portion; implanting a plurality of ions into the semiconductor substrate adjacent to the gate region of the NMOS portion to create an active region in the semiconductor substrate adjacent to the gate region of the NMOS portion, wherein said PMOS mask prevents the semiconductor substrate within said PMOS portion from being implanted with said plurality of ions; removing said PMOS mask over the PMOS portion; depositing a volume of an electrically conductive material selected from the group consisting of a silicon-containing material and a germanium-containing material and situated over the PMOS portion and the NMOS portion; forming a CMOS mask upon said volume of said electrically conductive material, and leaving an unmasked portion of said volume of said electrically conductive material that is positioned above the active region in the semiconductor substrate adjacent to the gate region of the NMOS portion; implanting a plurality of ions into the unmasked portion of said volume of said electrically conductive material to form therefrom a first portion thereof and also forming a second portion underlying the NMOS mask, the first portion having a concentration of said ions implanted therein that is greater than a concentration of ions implanted into the second portion; removing the CMOS mask upon said volume of said electrically conductive material; selectively removing said electrically conductive material by etching with a basic etchant from the second portion at a material removal rate that is greater than that of the first portion so as to remove the second portion and leave the first portion, said first portion forming an interconnect structure; forming a NMOS mask upon said interconnect structure and upon said gate region of said NMOS portion, and leaving the semiconductor substrate adjacent to the gate region of the PMOS portion unmasked; and implanting ions into the unmasked semiconductor substrate adjacent to the gate region of the PMOS portion so as to form an active region therein.

Claim 77

A method of forming an interconnect structure on a semiconductor substrate in a CMOS process flow, comprising: providing a semiconductor substrate having a PMOS portion thereon and an NMOS portion thereon, the PMOS portion and the NMOS portion each having a gate region formed therein; forming a PMOS mask over the PMOS portion; implanting a plurality of ions into the semiconductor substrate adjacent to the gate region of the NMOS portion to create an active region in the semiconductor substrate adjacent to the gate region of the NMOS portion, wherein said PMOS mask prevents the semiconductor substrate within said PMOS portion from being implanted with said plurality of ions; removing said PMOS mask over the PMOS portion; depositing a volume of an electrically conductive material selected from the group consisting of a silicon-containing material and a germanium-containing material and situated over the PMOS portion and the NMOS portion; forming a CMOS mask upon said volume of said electrically conductive material, and leaving an unmasked portion of said volume of said electrically conductive material that is positioned above the active region in the semiconductor substrate adjacent to the gate region of the NMOS portion; implanting a plurality of ions into the unmasked portion of said volume of said electrically conductive material to form therefrom a first portion thereof and also forming a second portion underlying the NMOS mask, the first portion having a concentration of said ions implanted therein that is greater than a concentration of ions implanted into the second portion; removing the CMOS mask upon said volume of said electrically conductive material; selectively removing said electrically conductive material by etching with a basic etchant from the second portion at a material removal rate that is greater than that of the first portion so as to remove the second portion and leave the first portion, said first portion forming an interconnect structure; forming a NMOS mask upon said interconnect structure and upon said gate region of said NMOS portion, and leaving the semiconductor substrate adjacent to the gate region of the PMOS portion unmasked; and implanting ions into the unmasked semiconductor substrate adjacent to the gate region of the PMOS portion so as to form an active region therein.

Claim 78

A method of forming a shaped structure on a semiconductor substrate, the method comprising: providing a volume of a material selected from the group consisting of a silicon-containing material and a germanium-containing material and extending from a planar surface on a semiconductor substrate, said volume of said material having thereon a side surface; implanting a plurality of ions into said side surface of said volume of said at a non-orthogonal angle to said planar surface on said semiconductor substrate to form within said volume of said material: a first portion; and a second portion, the first portion having a concentration of said ions implanted therein that is greater than a concentration of said ions that are implanted in the second portion; and selectively removing, by etching with a basic etchant, said material from the second implanted portion at a material removal rate that is greater than that of the first implanted portion to form a shaped structure extending from said planar surface on said semiconductor substrate.

Claim 79

A method of forming a shaped structure on a semiconductor substrate, the method comprising: providing a volume of a material selected from the group consisting of a silicon-containing material and a germanium-containing material and extending from a planar surface on a semiconductor substrate, said volume of said material having thereon a side surface; implanting a plurality of ions into said side surface of said volume of said at a non-orthogonal angle to said planar surface on said semiconductor substrate to form within said volume of said material: a first portion; and a second portion, the first portion having a concentration of said ions implanted therein that is greater than a concentration of said ions that are implanted in the second portion; and selectively removing, by etching with a basic etchant, said material from the second implanted portion at a material removal rate that is greater than that of the first implanted portion to form a shaped structure extending from said planar surface on said semiconductor substrate.

Claim 83

A method of forming a MOS surround-gate transistor on a semiconductor substrate, comprising: depositing a layer of a material selected from the group consisting of a silicon-containing material and a germanium-containing material on a planar surface of a semiconductor substrate; forming a mask on said layer of said material, said mask having an opening therein below which extends an unmasked portion of said layer of said material, said opening in said mask having a circular cross-section; anisotropically etching, using a basic etchant, said layer of said material to: remove therefrom said unmasked portion and to form: a volume of said material extending from said planar surface of said semiconductor substrate, said volume of said material having thereon a side surface; and a cylindrical void defined by the side surface of said volume of said material, said side surface being a continuous surface within said void; implanting a plurality of ions into said side surface of said volume of said material at a non-orthogonal angle to said planar surface on said semiconductor substrate to form in said volume of said material: a first portion; and a second portion, the first portion having a concentration of said ions implanted therein that is greater than a concentration of said ions implanted into the second portion; removing said mask; selectively removing, by etching with a basic etchant, said material from the second portion at a material removal rate that is greater than that of the first portion to form a gate region extending from said planar surface on said semiconductor substrate, said gate region having a outside surface opposite and parallel to said side surface, both said outside and side surfaces of said gate region being circular in cross section, said side surface of said gate region defining a circular surface on said semiconductor substrate; forming an insulating spacer on both said outside and side surfaces of said gate region, each said insulating spacer extending to terminate at the semiconductor substrate; and implanting dopants into the circular surface on said semiconductor substrate to form a first source/drain region and a second source/drain region, said second source/drain region being separated from said first source/drain region by said gate region and adjacent to the outside surface of said gate region.

Claim 84

A method of forming a MOS surround-gate transistor on a semiconductor substrate, comprising: depositing a layer of a material selected from the group consisting of a silicon-containing material and a germanium-containing material on a planar surface of a semiconductor substrate; forming a mask on said layer of said material, said mask having an opening therein below which extends an unmasked portion of said layer of said material, said opening in said mask having a circular cross-section; anisotropically etching, using a basic etchant, said layer of said material to: remove therefrom said unmasked portion and to form: a volume of said material extending from said planar surface of said semiconductor substrate, said volume of said material having thereon a side surface; and a cylindrical void defined by the side surface of said volume of said material, said side surface being a continuous surface within said void; implanting a plurality of ions into said side surface of said volume of said material at a non-orthogonal angle to said planar surface on said semiconductor substrate to form in said volume of said material: a first portion; and a second portion, the first portion having a concentration of said ions implanted therein that is greater than a concentration of said ions implanted into the second portion; removing said mask; selectively removing, by etching with a basic etchant, said material from the second portion at a material removal rate that is greater than that of the first portion to form a gate region extending from said planar surface on said semiconductor substrate, said gate region having a outside surface opposite and parallel to said side surface, both said outside and side surfaces of said gate region being circular in cross section, said side surface of said gate region defining a circular surface on said semiconductor substrate; forming an insulating spacer on both said outside and side surfaces of said gate region, each said insulating spacer extending to terminate at the semiconductor substrate; and implanting dopants into the circular surface on said semiconductor substrate to form a first source/drain region and a second source/drain region, said second source/drain region being separated from said first source/drain region by said gate region and adjacent to the outside surface of said gate region.

Claim 86

A method of forming a stacked capacitor storage node on a semiconductor substrate, the method comprising: providing a first volume of a material selected from the group consisting of a silicon-containing material and a germanium-containing material over a charge conducting region situated within a semiconductor substrate; forming on insulating layer over the first volume of the material; forming a first conical void extending through the insulating layer and the volume of the material to expose a surface on the charge conducting region, said first conical void being defined by an exposed inside surface; forming a second volume of the material on the exposed inside surface of the first conical void, thereby forming a second conical void within the first conical void, the second conical void being defined by an exposed surface on said second volume of the material that is situated within said first conical void; implanting a plurality of ions into the exposed surface on said second volume of said material that is situated within said first conical void to form an portion thereof having said ions implanted therein; removing a portion of the second volume of the material that is situated above the insulating layer by etching with a basic etchant; removing the insulating layer; and removing at least a portion of the first volume of the material, by etching with a basic etchant, at removal rate that is greater than that of said portion of said second volume of said material having said ions implanted therein, whereby a stacked capacitor storage node is formed extending from the charge conducting region.

Claim 87

A method of forming a stacked capacitor storage node on a semiconductor substrate, the method comprising: providing a first volume of a material selected from the group consisting of a silicon-containing material and a germanium-containing material over a charge conducting region situated within a semiconductor substrate; forming on insulating layer over the first volume of the material; forming a first conical void extending through the insulating layer and the volume of the material to expose a surface on the charge conducting region, said first conical void being defined by an exposed inside surface; forming a second volume of the material on the exposed inside surface of the first conical void, thereby forming a second conical void within the first conical void, the second conical void being defined by an exposed surface on said second volume of the material that is situated within said first conical void; implanting a plurality of ions into the exposed surface on said second volume of said material that is situated within said first conical void to form an portion thereof having said ions implanted therein; removing a portion of the second volume of the material that is situated above the insulating layer by etching with a basic etchant; removing the insulating layer; and removing at least a portion of the first volume of the material, by etching with a basic etchant, at removal rate that is greater than that of said portion of said second volume of said material having said ions implanted therein, whereby a stacked capacitor storage node is formed extending from the charge conducting region.

Claim 88

A method of forming a shaped structure on a semiconductor substrate, comprising: forming a mask extending from a volume of a material selected from the group consisting of a silicon-containing material and a germanium-containing material located on a planar surface of a semiconductor substrate; implanting a plurality of ions into the volume of the material and beneath the mask into the volume of the material so as to form therein a first and a second portion, the first portion having a concentration of said ions implanted therein that is greater than a concentration of said ions implanted in the second portion, the ions being implanted at least one angle that is non-orthogonal to the planar surface of the semiconductor substrate; removing said mask; and selectively removing, by etching with a basic etchant, said material from the second portion at a material removal rate that is greater than that of the first portion to form an opening in said volume of said material that terminates at said semiconductor substrate.

Claim 89

A method of forming a shaped structure on a semiconductor substrate, comprising: forming a mask extending from a volume of a material selected from the group consisting of a silicon-containing material and a germanium-containing material located on a planar surface of a semiconductor substrate; implanting a plurality of ions into the volume of the material and beneath the mask into the volume of the material so as to form therein a first and a second portion, the first portion having a concentration of said ions implanted therein that is greater than a concentration of said ions implanted in the second portion, the ions being implanted at least one angle that is non-orthogonal to the planar surface of the semiconductor substrate; removing said mask; and selectively removing, by etching with a basic etchant, said material from the second portion at a material removal rate that is greater than that of the first portion to form an opening in said volume of said material that terminates at said semiconductor substrate.

Claim 90

A method of forming an interconnect structure on a semiconductor substrate, comprising: providing a volume of an electrically conductive material selected from the group consisting of a silicon-containing material and a germanium-containing material situated over a charge conducting region located within a semiconductor substrate; masking the volume of the electrically conductive material with a mask to form a masked portion of the volume of the electrically conductive material situated above the charge conducting region and an unmasked portion of the volume of the electrically conductive material situated adjacent to the charge conducting region; reducing the height of the unmasked portion; implanting a plurality of ions into the volume of the electrically conductive material to form a first portion therein and also forming a second portion therein, the second portion being located within the masked portion of the volume of the electrically conductive material, the first portion having a concentration of said ions implanted therein that is greater than a concentration of said ions implanted in the second portion; removing the mask; and selectively removing, by etching with a basic etchant, said electrically conductive material from the first portion at a material removal rate that is greater than that of the second portion to form an interconnect structure from said volume of the electrically conductive material.

Claim 91

A method of forming an interconnect structure on a semiconductor substrate, comprising: providing a volume of an electrically conductive material selected from the group consisting of a silicon-containing material and a germanium-containing material situated over a charge conducting region located within a semiconductor substrate; masking the volume of the electrically conductive material with a mask to form a masked portion of the volume of the electrically conductive material situated above the charge conducting region and an unmasked portion of the volume of the electrically conductive material situated adjacent to the charge conducting region; reducing the height of the unmasked portion; implanting a plurality of ions into the volume of the electrically conductive material to form a first portion therein and also forming a second portion therein, the second portion being located within the masked portion of the volume of the electrically conductive material, the first portion having a concentration of said ions implanted therein that is greater than a concentration of said ions implanted in the second portion; removing the mask; and selectively removing, by etching with a basic etchant, said electrically conductive material from the first portion at a material removal rate that is greater than that of the second portion to form an interconnect structure from said volume of the electrically conductive material.

Claim 92

A method of forming a storage node of a stacked capacitor on a semiconductor substrate, comprising: forming a lower layer in an electrically insulated opening situated on a semiconductor substrate having a planar surface thereon; forming an intermediate layer upon the lower layer within the electrically insulated opening; forming an upper layer upon the intermediate layer within the electrically insulated opening, the upper, intermediate, and lower layers being composed of a material selected from the group consisting of a silicon-containing material and a germanium-containing material, the upper and lower layers being doped with an impurity, and the intermediate layer being undoped; implanting a plurality of ions through the upper layer into a segment of the intermediate layer that is parallel to the planar surface on the semiconductor substrate and that is located within the opening, so as to form a first and a second portion of said segment, the first portion having a concentration of said ions implanted therein that is greater than a concentration of said ions implanted in the second portion; and selectively removing, by etching with a basic etchant, said material from within said opening that is unimplanted with said ions and that is not doped with an impurity at a material removal rate that is greater than that of said material within said opening that is implanted with said ions and that is doped with said impurity, so as to form a storage node of a stacked capacitor that includes at least of portion of the upper and lower layers, and the first portion of said segment of the intermediate layer.

Claim 93

A method of forming a storage node of a stacked capacitor on a semiconductor substrate, comprising: forming a lower layer in an electrically insulated opening situated on a semiconductor substrate having a planar surface thereon; forming an intermediate layer upon the lower layer within the electrically insulated opening; forming an upper layer upon the intermediate layer within the electrically insulated opening, the upper, intermediate, and lower layers being composed of a material selected from the group consisting of a silicon-containing material and a germanium-containing material, the upper and lower layers being doped with an impurity, and the intermediate layer being undoped; implanting a plurality of ions through the upper layer into a segment of the intermediate layer that is parallel to the planar surface on the semiconductor substrate and that is located within the opening, so as to form a first and a second portion of said segment, the first portion having a concentration of said ions implanted therein that is greater than a concentration of said ions implanted in the second portion; and selectively removing, by etching with a basic etchant, said material from within said opening that is unimplanted with said ions and that is not doped with an impurity at a material removal rate that is greater than that of said material within said opening that is implanted with said ions and that is doped with said impurity, so as to form a storage node of a stacked capacitor that includes at least of portion of the upper and lower layers, and the first portion of said segment of the intermediate layer.

Claim 94

A method of forming a storage node of a stacked capacitor on a semiconductor substrate, comprising: forming an opening in an insulating layer situated on a planar surface of a semiconductor substrate, the opening extending from a top surface of said insulating layer to an exposed surface on a charge conducting region within said semiconductor substrate, said opening having a side surface on said insulating layer; forming a layer of a material selected from the group consisting of a silicon-containing material and a germanium-containing material on the side surface of the insulating layer within the opening and upon said exposed surface on said charge conducting region, such that layer of said material does not fill the opening; implanting a plurality of ions to a selected depth within the layer of the material in the opening to form therein a first portion and a second portion, the first portion having a concentration of said ions implanted therein that is greater than a concentration of said ions implanted in the second portion; filling the opening with a masking material; planarizing the insulating layer so as to remove a portion of the layer of the material that is situated outside of the opening in the insulating layer; removing the masking material within the opening; and selectively removing, by etching with a basic etchant, said material from the second portion at a material removal rate that is greater than that of the first portion to form from said portion of the layer of the material a storage node of a stacked capacitor on the semiconductor substrate, said storage node having a surface thereon that is orthogonal to the planar surface of said semiconductor substrate and is parallel to and physically separated from said side surface on said insulating layer within said opening.

Claim 95

A method of forming a storage node of a stacked capacitor on a semiconductor substrate, comprising: forming an opening in an insulating layer situated on a planar surface of a semiconductor substrate, the opening extending from a top surface of said insulating layer to an exposed surface on a charge conducting region within said semiconductor substrate, said opening having a side surface on said insulating layer; forming a layer of a material selected from the group consisting of a silicon-containing material and a germanium-containing material on the side surface of the insulating layer within the opening and upon said exposed surface on said charge conducting region, such that layer of said material does not fill the opening; implanting a plurality of ions to a selected depth within the layer of the material in the opening to form therein a first portion and a second portion, the first portion having a concentration of said ions implanted therein that is greater than a concentration of said ions implanted in the second portion; filling the opening with a masking material; planarizing the insulating layer so as to remove a portion of the layer of the material that is situated outside of the opening in the insulating layer; removing the masking material within the opening; and selectively removing, by etching with a basic etchant, said material from the second portion at a material removal rate that is greater than that of the first portion to form from said portion of the layer of the material a storage node of a stacked capacitor on the semiconductor substrate, said storage node having a surface thereon that is orthogonal to the planar surface of said semiconductor substrate and is parallel to and physically separated from said side surface on said insulating layer within said opening.

Claim 97

A method of forming a shaped structure on a semiconductor substrate, comprising: forming a first mask on a top surface of a volume of a material selected from a group consisting of a silicon-containing material and a germanium-containing material situated on a planar surface of a semiconductor substrate, wherein a masked portion of the volume of the material is masked by said first mask, and an unmasked portion of the volume of the material is not masked by said mask; implanting ions into the volume of the material within a first selected range extending from the top surface of said volume of the material to the semiconductor substrate to form therein: an ion concentration of said implanted ions in said unmasked portion; and an ion concentration of said implanted ions in said masked portion that is lower than that of said unmasked portion; removing the first mask; forming a second mask over the volume of the material located on the semiconductor substrate, wherein the unmasked portion of the volume of the material is masked by said second mask, and the masked portion of the volume of the material is unmasked by said second mask; implanting ions into the volume of the material to a second selected range extending from the top surface of said volume of the material to a level above the semiconductor substrate to form therein: a first ion implanted portion within said second selected range; and a second ion implanted portion extending from said first ion implanted portion to said planar surface on said semiconductor substrate and having an ion concentration of said implanted ions that is lower than that of said first ion implantation portion, wherein said first ion implanted portion of said masked portion has about the same ion concentration as that of the unmasked portion and the second ion implanted portion has an ion concentration of said implanted ions that is lower than that of the first ion implanted portion; removing the second mask; and selectively removing, by etching with a basic etchant, said material from the unmasked portion and the first ion implanted portion of said masked portion at a material removal rate that is greater than that of the second ion implanted portion of the masked portion to form a shaped structure comprising: said first ion implanted portion of said masked portion; and said unmasked portion, wherein said first ion implanted portion of said masked portion is in contact with said unmasked portion.

Claim 98

A method of forming a shaped structure on a semiconductor substrate, comprising: forming a first mask on a top surface of a volume of a material selected from a group consisting of a silicon-containing material and a germanium-containing material situated on a planar surface of a semiconductor substrate, wherein a masked portion of the volume of the material is masked by said first mask, and an unmasked portion of the volume of the material is not masked by said mask; implanting ions into the volume of the material within a first selected range extending from the top surface of said volume of the material to the semiconductor substrate to form therein: an ion concentration of said implanted ions in said unmasked portion; and an ion concentration of said implanted ions in said masked portion that is lower than that of said unmasked portion; removing the first mask; forming a second mask over the volume of the material located on the semiconductor substrate, wherein the unmasked portion of the volume of the material is masked by said second mask, and the masked portion of the volume of the material is unmasked by said second mask; implanting ions into the volume of the material to a second selected range extending from the top surface of said volume of the material to a level above the semiconductor substrate to form therein: a first ion implanted portion within said second selected range; and a second ion implanted portion extending from said first ion implanted portion to said planar surface on said semiconductor substrate and having an ion concentration of said implanted ions that is lower than that of said first ion implantation portion, wherein said first ion implanted portion of said masked portion has about the same ion concentration as that of the unmasked portion and the second ion implanted portion has an ion concentration of said implanted ions that is lower than that of the first ion implanted portion; removing the second mask; and selectively removing, by etching with a basic etchant, said material from the unmasked portion and the first ion implanted portion of said masked portion at a material removal rate that is greater than that of the second ion implanted portion of the masked portion to form a shaped structure comprising: said first ion implanted portion of said masked portion; and said unmasked portion, wherein said first ion implanted portion of said masked portion is in contact with said unmasked portion.

Claim 99

A method of forming a structure in a semiconductor substrate, comprising: forming a trench in a semiconductor substrate, said trench being defined by a sidewall on said semiconductor substrate that extends below a top surface of said semiconductor substrate; implanting a plurality of ions into the sidewall on said semiconductor substrate through the trench to form in said semiconductor substrate: a first portion; and a second portion, the first portion having a ion concentration of said implanted ions that is greater than a ion concentration of said implanted ions in the second portion; and selectively removing, by etching with a basic etchant, the first portion at a material removal rate that is greater than that of the second portion.

Claim 100

A method of forming a structure in a semiconductor substrate, comprising: forming a trench in a semiconductor substrate, said trench being defined by a sidewall on said semiconductor substrate that extends below a top surface of said semiconductor substrate; implanting a plurality of ions into the sidewall on said semiconductor substrate through the trench to form in said semiconductor substrate: a first portion; and a second portion, the first portion having a ion concentration of said implanted ions that is greater than a ion concentration of said implanted ions in the second portion; and selectively removing, by etching with a basic etchant, the first portion at a material removal rate that is greater than that of the second portion.

Claim 104

A method of selectively forming a layer of a material on an exposed horizontal surface of a semiconductor substrate, comprising: forming a raised structure extending from a planar surface on a semiconductor substrate, said raised structure having thereon a top surface parallel to said planar surface on the semiconductor substrate and a lateral surface orthogonal to said planar surface on the semiconductor substrate; forming a layer of a material selected from a group consisting of a silicon-containing material and a germanium-containing material upon the planar surface of the semiconductor substrate and over the top and lateral surfaces of said raised structure; implanting a plurality of ions into the layer of the material to form therein a first and a second portion, said ions being implanted orthogonal to the planar surface of the semiconductor substrate, said first portion being situated on the top surface of the raised structure and on the planar surface of the semiconductor substrate distal of said raised structure, said second portion being situated on said lateral surface and on said planar surface of semiconductor substrate proximal said raised structure; selectively removing, by etching with a basic etchant, said material from the second portion at a material removal rate that is greater than that of the first portion.

Claim 105

A method of selectively forming a layer of a material on an exposed horizontal surface of a semiconductor substrate, comprising: forming a raised structure extending from a planar surface on a semiconductor substrate, said raised structure having thereon a top surface parallel to said planar surface on the semiconductor substrate and a lateral surface orthogonal to said planar surface on the semiconductor substrate; forming a layer of a material selected from a group consisting of a silicon-containing material and a germanium-containing material upon the planar surface of the semiconductor substrate and over the top and lateral surfaces of said raised structure; implanting a plurality of ions into the layer of the material to form therein a first and a second portion, said ions being implanted orthogonal to the planar surface of the semiconductor substrate, said first portion being situated on the top surface of the raised structure and on the planar surface of the semiconductor substrate distal of said raised structure, said second portion being situated on said lateral surface and on said planar surface of semiconductor substrate proximal said raised structure; selectively removing, by etching with a basic etchant, said material from the second portion at a material removal rate that is greater than that of the first portion.

Claim 107

A method of forming an interconnect line on a semiconductor substrate, comprising: forming a volume of a material selected from a group consisting of a silicon-containing material and a germanium-containing material on a planar surface of a semiconductor substrate; forming a first mask over the volume of the material on the semiconductor substrate, wherein a masked portion of the volume of the material is masked by said first mask, and an unmasked portion of the volume of the material is not masked by said first mask; implanting ions into the volume of the material orthogonally to the planar surface on the semiconductor substrate so as to form therein: an ion concentration of said implanted ions in said unmasked portion; and an ion concentration of said implanted ions in said masked portion that is lower than that of said unmasked portion; removing the first mask; forming a second mask upon the volume of the material on the semiconductor substrate, wherein the second masked substrate defines a masked area on a top surface of the volume of the material on the semiconductor substrate, the masked area including the unmasked portion of the volume of the material; anisotropically etching with a basic etchant said material from the volume of the material on the semiconductor substrate at a material removal rate that is greater for said material having an implanted ion concentration that is below a selected threshold than that of said material having an implanted ion concentration above said selected threshold; and removing said second mask, whereby an interconnect structure composed of said material remains on said semiconductor substrate, said interconnect structure having a perimeter the same as the perimeter of the masked area.

Claim 108

A method of forming an interconnect line on a semiconductor substrate, comprising: forming a volume of a material selected from a group consisting of a silicon-containing material and a germanium-containing material on a planar surface of a semiconductor substrate; forming a first mask over the volume of the material on the semiconductor substrate, wherein a masked portion of the volume of the material is masked by said first mask, and an unmasked portion of the volume of the material is not masked by said first mask; implanting ions into the volume of the material orthogonally to the planar surface on the semiconductor substrate so as to form therein: an ion concentration of said implanted ions in said unmasked portion; and an ion concentration of said implanted ions in said masked portion that is lower than that of said unmasked portion; removing the first mask; forming a second mask upon the volume of the material on the semiconductor substrate, wherein the second masked substrate defines a masked area on a top surface of the volume of the material on the semiconductor substrate, the masked area including the unmasked portion of the volume of the material; anisotropically etching with a basic etchant said material from the volume of the material on the semiconductor substrate at a material removal rate that is greater for said material having an implanted ion concentration that is below a selected threshold than that of said material having an implanted ion concentration above said selected threshold; and removing said second mask, whereby an interconnect structure composed of said material remains on said semiconductor substrate, said interconnect structure having a perimeter the same as the perimeter of the masked area.

Claim 109

A method of forming an interconnect line on a semiconductor substrate, comprising: forming a volume of a material selected from a group consisting of a silicon-containing material and a germanium-containing material on a planar surface of a semiconductor substrate; forming a first mask over the volume of the material on the semiconductor substrate, wherein a masked portion of the volume of the material is masked by said first mask, and an unmasked portion of the volume of the material is not masked by said first mask; implanting ions into the volume of the material orthogonally to the planar surface on the semiconductor substrate so as to form therein: an ion concentration of said implanted ions in said unmasked portion; and an ion concentration of said implanted ions in said masked portion that is lower than that of said unmasked portion; removing the first mask; forming a second mask upon the volume of the material on the semiconductor substrate, wherein the second masked substrate defines a masked area on a top surface of the volume of the material on the semiconductor substrate, the masked area having a perimeter and including the unmasked portion of the volume of the material; anisotropically etching with a basic etchant said material from the volume of the material on the semiconductor substrate at a material removal rate that is greater for said material having an implanted ion concentration that is below a selected threshold than that of said material having an implanted ion concentration above said selected threshold, and wherein there is formed a lateral surface on the volume of the material on the semiconductor substrate that extends from the top surface of the volume of the material on the semiconductor substrate to the semiconductor substrate; implanting ions into the lateral surface of the volume of the material, the ions being implanted at least one angle that is non-orthogonal to the planar surface of the semiconductor substrate so as to form therein: an ion concentration of said implanted ions in a first implanted region that is outside of the perimeter of the masked area, and that is inside of and proximal to the perimeter of the masked area and beneath masked area; and an ion concentration of said implanted ions in a second implanted region that is beneath the masked area and distal of the perimeter of said masked area, wherein said first and second implanted regions extend from the top surface of the volume of the material on the semiconductor substrate to the semiconductor substrate, and wherein the ion concentration of the first implanted region is higher than that of the second implanted region; removing the second mask; selectively removing, by etching with a basic etchant, said material from the second implanted region at a material removal rate that is greater than that of the first implanted region, and selectively removing, by etching with a basic etchant, said material from the masked portion at a material removal rate that is greater than that of the unmasked portion, whereby there is formed an interconnect line from said material on the semiconductor substrate.

Claim 110

A method of forming an interconnect line on a semiconductor substrate, comprising: forming a volume of a material selected from a group consisting of a silicon-containing material and a germanium-containing material on a planar surface of a semiconductor substrate; forming a first mask over the volume of the material on the semiconductor substrate, wherein a masked portion of the volume of the material is masked by said first mask, and an unmasked portion of the volume of the material is not masked by said first mask; implanting ions into the volume of the material orthogonally to the planar surface on the semiconductor substrate so as to form therein: an ion concentration of said implanted ions in said unmasked portion; and an ion concentration of said implanted ions in said masked portion that is lower than that of said unmasked portion; removing the first mask; forming a second mask upon the volume of the material on the semiconductor substrate, wherein the second masked substrate defines a masked area on a top surface of the volume of the material on the semiconductor substrate, the masked area having a perimeter and including the unmasked portion of the volume of the material; anisotropically etching with a basic etchant said material from the volume of the material on the semiconductor substrate at a material removal rate that is greater for said material having an implanted ion concentration that is below a selected threshold than that of said material having an implanted ion concentration above said selected threshold, and wherein there is formed a lateral surface on the volume of the material on the semiconductor substrate that extends from the top surface of the volume of the material on the semiconductor substrate to the semiconductor substrate; implanting ions into the lateral surface of the volume of the material, the ions being implanted at least one angle that is non-orthogonal to the planar surface of the semiconductor substrate so as to form therein: an ion concentration of said implanted ions in a first implanted region that is outside of the perimeter of the masked area, and that is inside of and proximal to the perimeter of the masked area and beneath masked area; and an ion concentration of said implanted ions in a second implanted region that is beneath the masked area and distal of the perimeter of said masked area, wherein said first and second implanted regions extend from the top surface of the volume of the material on the semiconductor substrate to the semiconductor substrate, and wherein the ion concentration of the first implanted region is higher than that of the second implanted region; removing the second mask; selectively removing, by etching with a basic etchant, said material from the second implanted region at a material removal rate that is greater than that of the first implanted region, and selectively removing, by etching with a basic etchant, said material from the masked portion at a material removal rate that is greater than that of the unmasked portion, whereby there is formed an interconnect line from said material on the semiconductor substrate.