US5847419A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Si-SiGe semiconductor device and method of fabricating the same
Assignee: Toshiba Corp
•
Filing: 1997-09-16
•
Granted: 1998-12-08
•
Expires: 2017-09-16
Abstract
Abstract A semiconductor device comprises a semiconductor substrate, a first semiconductor layer under compressive strain formed on the semiconductor substrate, a p-type MISFET (Metal Insulator Semiconductor Field Effect Transistor) formed in a predetermined region of the first semiconductor layer, a second semiconductor layer in a lattice-relaxation condition formed on the first semiconductor layer in a region other than the predetermined region with an insulating film lying therebetween, wherein the insulating film has an opening and the first and second semiconductor layers are connected through the opening, a third semiconductor layer under tensile strain formed on the second semiconductor layer, and an n-type MISFET (Metal Insulator Semiconductor Field Effect Transistor) formed in the third semiconductor layer.
Inventors
- 👤 Seiji Imai
- 👤 Yoshiko Hiraoka
- 👤 Atsushi Kurobe
- 👤 Naoharu Sugiyama
- 👤 Tsutomu Tezuka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 08:26
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/67; H10D30/674; H10D30/6741; H10D30/6743; H10D30/6744; H10D84/00; H10D84/01; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/856; H10D86/00; H10D86/01; H10D88/00
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
114 words
A semiconductor device comprising: a semiconductor substrate; a first semiconductor layer under compressive strain formed on the semiconductor substrate; a p-type MISFET (Metal Insulator Semiconductor Field Effect Transistor) formed in a predetermined region of the first semiconductor layer; a second semiconductor layer in a lattice-relaxation condition formed on the first semiconductor layer in a region other than the predetermined region with an insulating film lying therebetween, wherein the insulating film has an opening and the first and second semiconductor layers are connected through the opening; a third semiconductor layer under tensile strain formed on the second semiconductor layer; and an n-type MISFET (Metal Insulator Semiconductor Field Effect Transistor) formed in the third semiconductor layer.
Claim 2
Dependent Claim
114 words
A semiconductor device comprising: a semiconductor substrate; a first semiconductor layer under compressive strain formed on the semiconductor substrate; a p-type MISFET (Metal Insulator Semiconductor Field Effect Transistor) formed in a predetermined region of the first semiconductor layer; a second semiconductor layer in a lattice-relaxation condition formed on the first semiconductor layer in a region other than the predetermined region with an insulating film lying therebetween, wherein the insulating film has an opening and the first and second semiconductor layers are connected through the opening; a third semiconductor layer under tensile strain formed on the second semiconductor layer; and an n-type MISFET (Metal Insulator Semiconductor Field Effect Transistor) formed in the third semiconductor layer.
Claim 3
Independent Claim
151 words
A method of fabricating a semiconductor device comprising the steps of: providing a semiconductor substrate; forming a first semiconductor layer under compressive strain on the semiconductor substrate; forming an insulating film having an opening on the first semiconductor layer; depositing a semiconductor layer having an amorphous silicon-germanium as a principal component on the insulating film; forming a second semiconductor layer in a lattice-relaxation condition by subjecting the semiconductor layer having the amorphous silicon-germanium as a principal component to a heat treatment; forming a third semiconductor layer under tensile strain on the second semiconductor layer; removing parts of the third and second semiconductor layers; forming a p-type MISFET (Metal Insulator Semiconductor Field Effect Transistor) in a region of the first semiconductor layer exposed after the parts of the third and second semiconductor layers have been removed; and forming an n-type MISFET (Metal Insulator Semiconductor Field Effect Transistor) in the third semiconductor layer.
Claim 4
Independent Claim
151 words
A method of fabricating a semiconductor device comprising the steps of: providing a semiconductor substrate; forming a first semiconductor layer under compressive strain on the semiconductor substrate; forming an insulating film having an opening on the first semiconductor layer; depositing a semiconductor layer having an amorphous silicon-germanium as a principal component on the insulating film; forming a second semiconductor layer in a lattice-relaxation condition by subjecting the semiconductor layer having the amorphous silicon-germanium as a principal component to a heat treatment; forming a third semiconductor layer under tensile strain on the second semiconductor layer; removing parts of the third and second semiconductor layers; forming a p-type MISFET (Metal Insulator Semiconductor Field Effect Transistor) in a region of the first semiconductor layer exposed after the parts of the third and second semiconductor layers have been removed; and forming an n-type MISFET (Metal Insulator Semiconductor Field Effect Transistor) in the third semiconductor layer.
Claim 5
Dependent Claim
48 words
A method of fabricating a semiconductor device according to claim 2, wherein said insulating film forming step includes substeps of forming a semiconductor layer having a silicon as a principal component on the first semiconductor layer, and oxidizing the semiconductor layer having the silicon as a principal component.
Claim 6
Dependent Claim
47 words
A method of fabricating a semiconductor device according to claim 2, wherein said semiconductor layer depositing step includes substeps of forming a semiconductor epitaxial layer having crystal silicon-germanium as a principal component in the opening, and forming a semiconductor layer having amorphous silicon-germanium as a principal component.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-12-07 | 2002-06-08 | 2002-12-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-12-07 | 2006-06-08 | 2006-12-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-12-07 | 2010-06-08 | 2010-12-08 | $7700.00 | Window Closed / Lapsed |