US5268324A
Expired / Lapsed
US
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Modified silicon CMOS process having selectively deposited Si/SiGe FETS
Assignee: GlobalFoundries Inc
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Filing: 1992-05-27
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Granted: 1993-12-07
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Expires: 2012-05-27
Abstract
Abstract A process is disclosed for making CMOS devices with enhanced performance PMOS FETS by integrating germanium technology into a silicon-based fabrication method. Silicon-germanium layers are selectively grown on the surfaces of oxide-isolated PFET pockets of a silicon substrate previously prepared by a conventional silicon CMOS process. A silicon cap is deposited over each Si--Ge layer and gate insulator is formed over the cap provide gate dielectric for the PFETS. Gate insulator is formed over the NFET pockets to provide gate dielectric for the NFETS. Gate structures are completed along with source and drain junctions in accordance with normal practice. Provision also is made for the additional selective growth of a second silicon-germanium layer on the surfaces of oxide-isolated NFET pockets on the same CMOS substrate to enhance the performance of the NFETS as well as that of the PFETS.
Inventors
- 👤 John M. Aitken
- 👤 Vijay P. Kesan
- 👤 Seshadri Subbanna
- 👤 Manu J. Tejwani
- 👤 Subramanian S. Iyer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 20:18
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/02; H10D84/03; H10D84/038; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/859; Y; Y10; Y10S; Y10S148/00; Y10S148/082; Y10S438/00; Y10S438/902
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
116 words
A process for making CMOS devices comprising: forming recessed oxide-isolated regions of a silicon substrate for PFETS and NFETS, respectively, said regions being oppositely doped relative to each other to accommodate said PFETS and NFETS, respectively, selectively depositing only on the surface of each of said regions associated with said PFETS a channel layer comprising a silicon-germanium layer covered by a silicon capping layer, forming a dielectric on said capping layer and over each of said regions associated with said NFETS, forming a conductive gate member over said oxide in each of said regions to complete the gate structures of said PFETS and NFETS, and forming source and drain regions adjacent each of said gate members.
Claim 2
Dependent Claim
116 words
A process for making CMOS devices comprising: forming recessed oxide-isolated regions of a silicon substrate for PFETS and NFETS, respectively, said regions being oppositely doped relative to each other to accommodate said PFETS and NFETS, respectively, selectively depositing only on the surface of each of said regions associated with said PFETS a channel layer comprising a silicon-germanium layer covered by a silicon capping layer, forming a dielectric on said capping layer and over each of said regions associated with said NFETS, forming a conductive gate member over said oxide in each of said regions to complete the gate structures of said PFETS and NFETS, and forming source and drain regions adjacent each of said gate members.
Claim 3
Dependent Claim
30 words
The process defined in claim 1 wherein said dielectric is formed by simultaneously oxidizing said capping layer and the silicon surface of each of said regions associated with said NFETS.
Claim 4
Dependent Claim
20 words
The process defined in claim 1 wherein said silicon-germanium layer composition is within the range defined by Si.sub.1-x Ge.sub.x (0≦×≦0.25)
Claim 5
Dependent Claim
25 words
The process defined in claim 3 wherein the thickness of said silicon-germanium layer is within the range of about 125 Å to about 300 Å.
Claim 6
Dependent Claim
134 words
A process for making CMOS devices comprising: forming recessed oxide-isolated regions of a silicon substrate for PFETS and NFETS, respectively, said regions being oppositely doped relative to each other to accommodate said PFETS and NFETS, respectively, selectively depositing on the surface of each of said regions associated with said PFETS a first channel layer comprising a silicon-germanium layer covered by a silicon capping layer, subsequently selectively depositing on the surface of each of said regions associated with said NFETS a second channel layer comprising a silicon-germanium layer covered by a silicon capping layer, forming a dielectric on said capping layers, forming a conductive gate member over said dielectric in each said region to complete the gate structures of said PFETS and NFETS, and forming source and drain regions adjacent each of said gate members.
Claim 7
Dependent Claim
134 words
A process for making CMOS devices comprising: forming recessed oxide-isolated regions of a silicon substrate for PFETS and NFETS, respectively, said regions being oppositely doped relative to each other to accommodate said PFETS and NFETS, respectively, selectively depositing on the surface of each of said regions associated with said PFETS a first channel layer comprising a silicon-germanium layer covered by a silicon capping layer, subsequently selectively depositing on the surface of each of said regions associated with said NFETS a second channel layer comprising a silicon-germanium layer covered by a silicon capping layer, forming a dielectric on said capping layers, forming a conductive gate member over said dielectric in each said region to complete the gate structures of said PFETS and NFETS, and forming source and drain regions adjacent each of said gate members.
Claim 8
Dependent Claim
16 words
The process defined in claim 3 wherein said oxide is formed by oxidizing said capping layers.
Claim 9
Dependent Claim
27 words
The process defined in claim 5 wherein the composition of said silicon-germanium layer of said first channel layer is within the range defined by Si.sub.1-x Ge.sub.x (0≦×≦0.25).
Claim 10
Dependent Claim
30 words
The process defined in claim 7 wherein the thickness of said silicon-germanium layer of said first channel layer is within the range of about 125 Å to about 300 Å.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1996-12-06 | 1997-06-07 | 1997-12-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-12-06 | 2001-06-07 | 2001-12-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-12-06 | 2005-06-07 | 2005-12-07 | $7700.00 | Window Closed / Lapsed |