Method for the manufacture of complementary MOS field effect transistors in VLSI technology

Claim 1

A method for the manufacture of a complementary MOS field effect transistor which comprises: (a) providing a silicon substrate doped with a dopant of a first conductivity type, said substrate having n-wells or p-wells formed therein, field oxide regions separating the active transistor regions, channel implantation regions for n-channel and p-channel transistors and a gate region for the transistors already defined; (b) depositing a first SiO 2 layer on said substrate to a thickness corresponding to the spacer oxide width of the gate of the p-channel transistor to be later generated; (c) depositing a silicon nitride layer on said substrate to form a double layer of SiO 2 and silicon nitride; (d) structuring said double layer so that p-channel regions remain covered by said double layer; (e) thermally oxidizing the resulting substrate; (f) implanting ions for forming an n-channel transistor; (g) depositing a second SiO 2 layer and anisotropically etching the same such that oxide regions remain at the side walls of the n-channel gate electrodes; (h) carrying out source/drain ion implantations for generating the n-channel transistors; (i) applying a photo-resist mask onto the n-channel regions not covered by said double layer and removing the remaining second SiO 2 layer in the p-channel region by isotropic over-etching, (j) removing said silicon nitride layer; (k) anisotropically re-etching said first SiO 2 layer such that oxide regions remain at the side walls of said gate electrodes in the p-channel region and a residual oxide of less than 50 nm remains on the active transistor regions; (l) carrying out source/drain ion implantation for generating p-channel transistors; and (m) forming metallic electrodes extending to said active transistor regions.

Claim 2

A method for the manufacture of a complementary MOS field effect transistor which comprises: (a) providing a silicon substrate doped with a dopant of a first conductivity type, said substrate having n-wells or p-wells formed therein, field oxide regions separating the active transistor regions, channel implantation regions for n-channel and p-channel transistors and a gate region for the transistors already defined; (b) depositing a first SiO 2 layer on said substrate to a thickness corresponding to the spacer oxide width of the gate of the p-channel transistor to be later generated; (c) depositing a silicon nitride layer on said substrate to form a double layer of SiO 2 and silicon nitride; (d) structuring said double layer so that p-channel regions remain covered by said double layer; (e) thermally oxidizing the resulting substrate; (f) implanting ions for forming an n-channel transistor; (g) depositing a second SiO 2 layer and anisotropically etching the same such that oxide regions remain at the side walls of the n-channel gate electrodes; (h) carrying out source/drain ion implantations for generating the n-channel transistors; (i) applying a photo-resist mask onto the n-channel regions not covered by said double layer and removing the remaining second SiO 2 layer in the p-channel region by isotropic over-etching, (j) removing said silicon nitride layer; (k) anisotropically re-etching said first SiO 2 layer such that oxide regions remain at the side walls of said gate electrodes in the p-channel region and a residual oxide of less than 50 nm remains on the active transistor regions; (l) carrying out source/drain ion implantation for generating p-channel transistors; and (m) forming metallic electrodes extending to said active transistor regions.