Cmos devices and method of manufacturing the same

Claim 1

We Claim:

Claim 2

The method of forming a semiconductor structure in and on a substrate having an N region and a P region each extending to the surface of the substrate and a first gate formed above a portion of the P region and a second gate formed above a portion of the N region, the method comprising: forming a first and a second N - source/drain region in the P region separated by a channel portion of the P region underlying the first gate; forming a first and a second sidewall spacer having a first selected width abutting the respective ends of the second gate; forming a first and a second P source/drain region in the N region separated by a channel portion of the N region underlying the second gate; forming a third and a fourth sidewall spacer having a second selected width abutting the ends of the first gate; forming a first and a second N + source/drain region within the first and the second N - source drain regions, respectively; annealing after forming the first and second P + source/drain regions and the first and second N source/drain regions, wherein the first width is selected to be sufficiently narrow so that after the annealing, the P + source/drain regions do not underlap the second gate, and wherein the second width is selected sufficiently wide so that after annealing, a portion of the first N source/drain region overlaps the first gate and separates the first N source/drain region from the channel portion of the P region and a portion of the second N - source/drain region overlaps the first gate and separates the second N + source/drain region from the channel portion of the P region and the N + source/drain regions are laterally separated from the first gate.