US4994866A
Expired / Lapsed
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Complementary semiconductor device
Assignee: Fujitsu Ltd
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Filing: 1989-01-05
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Granted: 1991-02-19
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Expires: 2009-01-05
Abstract
Abstract A complementary semiconductor device (CMOS gate) including a p-channel transistor (PMOS FET) and an n-channel transistor (NMOS FET). A silicon substrate, a channel layer for the p-channel transistor which comprises a first Si 1-x Ge x layer, a Ge layer, and a second Si 1-x Ge x layer are formed in sequence on the silicon substrate. A silicon layer, as another channel layer for the n-channel transistor, is formed on the channel layer. The ratio "x" of the first Si 1-x Ge x layer is continuously increased from 0 to 1, and the ratio "x" of the second Si 1-x Ge x layer is continuously decreased from 1 to 0.
Inventors
- 👤 Yuji Awano
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 02:16
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/80; H10D62/82; H10D62/822; H10D30/00; H10D30/40; H10D30/47; H10D30/471; H10D30/473; H10D30/60; H10D30/751; H10D30/80; H10D30/801; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0158; H10D84/0165; H10D84/0167; H10D84/0193; H10D84/02; H10D84/03; H10D84/038; H10D84/80; H10D84/82; H10D84/83; H10D84/85
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
66 words
A complementary semiconductor device including a p-channel transistor and an n-channel transistor comprising: a silicon substrate; a channel layer for the p-channel transistor comprising a first Si 1-x Ge x layer, a Ge layer, and a second Si 1-x Ge x layer formed in sequence on said silicon substrate; and another channel layer for the n-channel transistor comprising a silicon layer formed on said channel layer.
Claim 2
Dependent Claim
66 words
A complementary semiconductor device including a p-channel transistor and an n-channel transistor comprising: a silicon substrate; a channel layer for the p-channel transistor comprising a first Si 1-x Ge x layer, a Ge layer, and a second Si 1-x Ge x layer formed in sequence on said silicon substrate; and another channel layer for the n-channel transistor comprising a silicon layer formed on said channel layer.
Claim 3
Dependent Claim
26 words
A complementary semiconductor device according to claim 1, wherein the ratio "x" of said first Si 1-x Ge x layer continuously varies from 0 to 1.
Claim 4
Dependent Claim
26 words
a complementary semiconductor device according to claim 1, wherein the ratio "x" of said second Si 1-x Ge x layer continuously varies from 1 to 0.
Claim 5
Dependent Claim
23 words
A complementary semiconductor device according to claim 1, wherein said Ge layer consists of from 90% to 100% Ge and the rest Si.
Claim 6
Dependent Claim
27 words
A complementary semiconductor device according to claim 1, wherein said silicon substrate is i-type or p-type, said Ge layer is p-type, and said silicon layer is p-type.
Claim 7
Dependent Claim
21 words
A complementary semiconductor device according to claim 5, wherein each of said first and second SiGe layers is p-type or i-type.
Claim 8
Dependent Claim
31 words
A complementary semiconductor device according to claim 1, wherein each of said silicon substrate, said first SiGe layer, said Ge layer, said second SiGe layer, and said silicon layer is i-type.
Claim 9
Dependent Claim
98 words
A complementary semiconductor device according to claim 1, wherein: said p-channel transistor comprises a source region and a drain region, each thereof formed by doping p-type impurities into said silicon substrate through the silicon layer and the channel layer; said n-channel transistor comprises another source region and another drain region, each thereof formed by doping n-type impurities into said channel layer through the silicon layer; and said device further comprises an isolation region isolating said p-channel transistor and said n-channel transistor from each other and extending to said silicon substrate through said silicon layer and said channel layer.
Claim 10
Dependent Claim
47 words
A complementary semiconductor device according to claim 8, wherein said p-channel transistor further comprises: a gate insulating layer formed on said silicon layer between said source and drain regions of said p-channel transistor; and source and drain electrodes respectively in contact with said source and drain regions.
Claim 11
Dependent Claim
49 words
A complementary semiconductor device according to claim 8, wherein said n-channel transistor further comprises: a gate insulating layer formed on said silicon layer between said another source and drain regions of said n-channel transistor; and source and drain electrodes respectively in contact with said another source and drain regions.
Claim 12
Dependent Claim
13 words
A complementary semiconductor device according to claim 1 forming a CMOS inverter gate.
Claim 13
Dependent Claim
139 words
A complementary semiconductor device including a p-channel transistor and an n-channel transistor comprising: a silicon substrate having a main surface with a first region and a second region defined at said main surface thereof; a channel layer for the p-channel transistor comprising a first Si 1-x Ge x layer, a Ge layer, and a second Si 1-x Ge x layer formed in sequence on said first and second regions; another channel layer for the n-channel transistor comprising a silicon layer formed on said channel layer formed over said first and second regions; a first gate insulating layer and a first gate electrode formed on said silicon layer above said first region, for the p-channel transistor; and a second gate insulating layer and a second gate electrode formed on said silicon layer above said second region, for the n-channel transistor.
Claim 14
Dependent Claim
139 words
A complementary semiconductor device including a p-channel transistor and an n-channel transistor comprising: a silicon substrate having a main surface with a first region and a second region defined at said main surface thereof; a channel layer for the p-channel transistor comprising a first Si 1-x Ge x layer, a Ge layer, and a second Si 1-x Ge x layer formed in sequence on said first and second regions; another channel layer for the n-channel transistor comprising a silicon layer formed on said channel layer formed over said first and second regions; a first gate insulating layer and a first gate electrode formed on said silicon layer above said first region, for the p-channel transistor; and a second gate insulating layer and a second gate electrode formed on said silicon layer above said second region, for the n-channel transistor.
References Cited (Backward Citations)
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