Low power AlGaAs/GaAs complementary FETs incorporating InGaAs n-channel gates

Claim 2

A lower planar complementary GaAs based heterostructure integrated circuit structure comprising: semi-insulating GaAs substrate means having a flat major surface; planar epitaxial grown intrinsic layers sequentially grown in order over said flat major surface comprising a first epitaxially grown layer of intrinsic GaAs grown directly over said surface, said GaAs layer having high mobility and having a first bandgap; a second epitaxially grown layer of intrinsic (Al,Ga)As grown directly over said first layer, which i-(Al,Ga)As has a larger bandgap than said first bandgap, and in which the energy gap difference is divided between valence and conduction bands; a heavily doped In y Ga 1-y As (where 0<y<0.2) thin layer epitaxially grown on the final layer of said intrinsic layers and defining the location of a first gate electrode; a first metal gate electrode deposited on said In y Ga 1-y As; a second metal gate electrode deposited on the surface of the final layer of said intrinsic layers; a n + source and a n + drain region in said structure defined by selective donor ion implantation into said structure next to said first gate electrode; a p + source and a p + drain region in said structure defined by selective acceptor ion implantation into said structure next to said second gate electrode; first and second n-ohmic contacts alloyed to said n-source and n-drain regions, respectively; and, third and fourth p-ohmic contacts alloyed to said p-source and p-drain regions, respectively.

Claim 3

The structure according to claim 1 in which said In y Ga 1-y As is of a thickness in the range of 200 to 500 Å.

Claim 4

A low-power planar complementary GaAs based heterostructure integrated circuit structure having complementary self-aligned gate (Al,Ga)As/GaAs heterostructure devices with an insulating (Al,Ga)As (SAG) gate structure to form CMOS-like GaAs IC's, the planar complementary IC structure comprising: semi-insulating GaAs substrate means having a flat major surface; a first MBE grown layer of intrinsic GaAs grown directly over said surface, said GaAs layer having high mobility and having a first bandgap; a second MBE grown layer of intrinsic (Al,Ga)As grown directly over said layer of i-GaAs, which i-(Al-Ga)As has a larger bandgap than said first bandgap, and in which the energy gap difference is divided between valence and conduction bands; a MBE grown thin-layer of heavily doped In y Ga 1-y As (where 0<y<0.2) on the layer of i-(Al,Ga)As and defining the location of a first gate electrode; a first metal gate electrode deposited on the surface of the In y Ga 1-y As; a second metal gate electrode deposited on the surface of said i-(Al,Ga)As layer; a n + source and a n + drain region defined by selective donor ion implantation in said structure next to said first gate electrode; a p + source and a p + drain region defined by selective acceptor ion implantation in said structure next to said second gate electrode; first and second n-ohmic contacts alloyed to said n-source and n-drain regions, respectively; and, third and fourth p-ohmic contacts alloyed to said p-source and p-drain regions, respectively.

Claim 5

A low-power planar complementary GaAs based heterostructure integrated circuit structure having complementary self-aligned gate (Al,Ga)As/GaAs heterostructure devices with an insulating (Al,Ga)As (SAG) gate structure to form CMOS-like GaAs IC's, the planar complementary IC structure comprising: semi-insulating GaAs substrate means having a flat major surface; a first MBE grown layer of intrinsic GaAs grown directly over said surface, said GaAs layer having high mobility and having a first bandgap; a second MBE grown layer of intrinsic (Al,Ga)As grown directly over said layer of i-GaAs, which i-(Al-Ga)As has a larger bandgap than said first bandgap, and in which the energy gap difference is divided between valence and conduction bands; a MBE grown thin-layer of heavily doped In y Ga 1-y As (where 0<y<0.2) on the layer of i-(Al,Ga)As and defining the location of a first gate electrode; a first metal gate electrode deposited on the surface of the In y Ga 1-y As; a second metal gate electrode deposited on the surface of said i-(Al,Ga)As layer; a n + source and a n + drain region defined by selective donor ion implantation in said structure next to said first gate electrode; a p + source and a p + drain region defined by selective acceptor ion implantation in said structure next to said second gate electrode; first and second n-ohmic contacts alloyed to said n-source and n-drain regions, respectively; and, third and fourth p-ohmic contacts alloyed to said p-source and p-drain regions, respectively.

Claim 6

The structure according to claim 3 in which said In y Ga 1-y As is of a thickness in the range of 200 to 500 Å.

Claim 7

A complementary, planar heterostructure IC in which both the n-channel and p-channel transistors utilize a 2D electron (hole) gas in an undoped high mobility channel to form CMOS-like IC's, the complementary, planar IC structure comprising: semi-insulating GaAs substrate means having a flat major surface; a first epitaxially grown layer of intrinsic GaAs over said surface, said GaAs layer having high mobility and having a first bandgap; a second epitaxially grown layer of intrinsic (Al,Ga)As over said first layer, which i-(Al,Ga)As has a larger bandgap than said first bandgap, and in which the energy gap difference is divided between valence and conduction bands; a third epitaxially grown layer of intrinsic GaAs over said second layer; a fourth epitaxially grown area of highly doped In y Ga 1-y As on said third layer and defining the location of a first gate electrode; a first metal gate electrode deposited on said In y Ga 1-y As; a second metal gate electrode deposited on the surface of said third epitaxial layer; a n + source and a n + drain region defined by selective donor ion implantation in said structure next to said first gate electrode; a p + source and a p + drain region defined by selective acceptor ion implantation in said structure next to said second gate electrode; first and second n-ohmic contacts alloyed to said n-source and n-drain regions, respectively; and, third and fourth p-ohmic contacts alloyed to said p-source and p-drain regions, respectively.

Claim 8

A complementary, planar heterostructure IC in which both the n-channel and p-channel transistors utilize a 2D electron (hole) gas in an undoped high mobility channel to form CMOS-like IC's, the complementary, planar IC structure comprising: semi-insulating GaAs substrate means having a flat major surface; a first epitaxially grown layer of intrinsic GaAs over said surface, said GaAs layer having high mobility and having a first bandgap; a second epitaxially grown layer of intrinsic (Al,Ga)As over said first layer, which i-(Al,Ga)As has a larger bandgap than said first bandgap, and in which the energy gap difference is divided between valence and conduction bands; a third epitaxially grown layer of intrinsic GaAs over said second layer; a fourth epitaxially grown area of highly doped In y Ga 1-y As on said third layer and defining the location of a first gate electrode; a first metal gate electrode deposited on said In y Ga 1-y As; a second metal gate electrode deposited on the surface of said third epitaxial layer; a n + source and a n + drain region defined by selective donor ion implantation in said structure next to said first gate electrode; a p + source and a p + drain region defined by selective acceptor ion implantation in said structure next to said second gate electrode; first and second n-ohmic contacts alloyed to said n-source and n-drain regions, respectively; and, third and fourth p-ohmic contacts alloyed to said p-source and p-drain regions, respectively.

Claim 9

The structure according to claim 5 in which said In y Ga 1-y As is of a thickness in the range of 200 to 500 Å.

Claim 10

A low-power planar complementary GaAs based heterostructure integrated circuit structure comprising: semi-insulating GaAs substrate means having a flat major surface; planar epitaxial grown intrinsic layers sequentially grown in order over said flat major surface comprising a first epitaxially grown layer of intrinsic GaAs grown directly over said surface, said GaAs layer having high mobility and having a first bandgap; a second epitaxially grown layer of intrinsic (Al,Ga)As grown directly over said first layer, which i-(Al,Ga)As has a larger bandgap than said first bandgap, and in which the energy gap difference is divided between valence and conduction bands; a heavily doped In y Ga 1-y As (where 0<y<0.2) thin layer of a thickness of less than about 1000 Å epitaxially grown on the final layer of said intrinsic layers and defining the location of a first gate electrode; a first metal gate electrode deposited on said In y Ga 1-y As; a second metal gate electrode deposited on the surface of the final layer of said intrinsic layers; a n + source and a n + drain region in said structure defined by selective donor ion implantation into said structure next to said first gate electrode; a p + source and a p + drain region in said structure defined by selective acceptor ion implantation into said structure next to said second gate electrode; first and second n-ohmic contacts alloyed to said n-source and n-drain regions, respectively; and, third and fourth p-ohmic contacts alloyed to said p-source and p-drain regions, respectively.

Claim 11

A low-power planar complementary GaAs based heterostructure integrated circuit structure comprising: semi-insulating GaAs substrate means having a flat major surface; planar epitaxial grown intrinsic layers sequentially grown in order over said flat major surface comprising a first epitaxially grown layer of intrinsic GaAs grown directly over said surface, said GaAs layer having high mobility and having a first bandgap; a second epitaxially grown layer of intrinsic (Al,Ga)As grown directly over said first layer, which i-(Al,Ga)As has a larger bandgap than said first bandgap, and in which the energy gap difference is divided between valence and conduction bands; a heavily doped In y Ga 1-y As (where 0<y<0.2) thin layer of a thickness of less than about 1000 Å epitaxially grown on the final layer of said intrinsic layers and defining the location of a first gate electrode; a first metal gate electrode deposited on said In y Ga 1-y As; a second metal gate electrode deposited on the surface of the final layer of said intrinsic layers; a n + source and a n + drain region in said structure defined by selective donor ion implantation into said structure next to said first gate electrode; a p + source and a p + drain region in said structure defined by selective acceptor ion implantation into said structure next to said second gate electrode; first and second n-ohmic contacts alloyed to said n-source and n-drain regions, respectively; and, third and fourth p-ohmic contacts alloyed to said p-source and p-drain regions, respectively.

Claim 12

A low-power planar complementary GaAs based heterostructure integrated circuit structure comprising: semi-insulating GaAs substrate means having a flat major surface; planar epitaxial grown intrinsic layers sequentially grown in order over said flat major surface comprising a first epitaxially grown layer of intrinsic GaAs grown directly over said surface, said GaAs layer having high mobility and having a first bandgap; a second epitaxially grown layer of intrinsic (Al,Ga)As grown directly over said first layer, which i-(Al,Ga)As has a larger bandgap than said first bandgap, and in which the energy gap difference is divided between valence and conduction bands; a heavily doped In y Ga 1-y As (where y is a fraction on the order of 0.15) thin layer epitaxially grown on the final layer of said intrinsic layers and defining the location of a first gate electrode; a first metal gate electrode deposited on said In y Ga 1-y As; a second metal gate electrode deposited on the surface of the final layer of said intrinsic layers; a n + source and a n + drain region in said structure defined by selective donor ion implantation into said structure next to said first gate electrode; a p + source and a p + drain region in said structure defined by selective acceptor ion implantation into said structure next to said second gate electrode; first and second n-ohmic contacts alloyed to said n-source and n-drain regions, respectively; and, third and fourth p-ohmic contacts alloyed to said p-source and p-drain region, respectively.

Claim 13

A low-power planar complementary GaAs based heterostructure integrated circuit structure comprising: semi-insulating GaAs substrate means having a flat major surface; planar epitaxial grown intrinsic layers sequentially grown in order over said flat major surface comprising a first epitaxially grown layer of intrinsic GaAs grown directly over said surface, said GaAs layer having high mobility and having a first bandgap; a second epitaxially grown layer of intrinsic (Al,Ga)As grown directly over said first layer, which i-(Al,Ga)As has a larger bandgap than said first bandgap, and in which the energy gap difference is divided between valence and conduction bands; a heavily doped In y Ga 1-y As (where y is a fraction on the order of 0.15) thin layer epitaxially grown on the final layer of said intrinsic layers and defining the location of a first gate electrode; a first metal gate electrode deposited on said In y Ga 1-y As; a second metal gate electrode deposited on the surface of the final layer of said intrinsic layers; a n + source and a n + drain region in said structure defined by selective donor ion implantation into said structure next to said first gate electrode; a p + source and a p + drain region in said structure defined by selective acceptor ion implantation into said structure next to said second gate electrode; first and second n-ohmic contacts alloyed to said n-source and n-drain regions, respectively; and, third and fourth p-ohmic contacts alloyed to said p-source and p-drain region, respectively.

Claim 14

A low-power planar complementary GaAs based heterostructure integrated circuit structure comprising: semi-insulating GaAs substrate means having a flat major surface; planar epitaxial grown intrinsic layers sequentially grown in order over said flat major surface comprising a first epitaxially grown layer of intrinsic GaAs grown directly over said surface, said GaAs layer having high mobility and having a first bandgap; a second epitaxially grown layer of intrinsic (Al,Ga)As grown directly over said first layer, which i-(Al,Ga)As has a larger bandgap than said first bandgap, and in which the energy gap difference is divided between valence and conduction bands; a heavily doped In y Ga 1-y As (where 0<y<0.2) thin layer epitaxially grown on the final layer of said intrinsic layers and defining the location of a first gate electrode; a first metal gate electrode deposited on said In y Ga 1- As; a second metal gate electrode deposited on the surface of the final layer of said intrinsic layers, in which said first and second metal gate electrodes are of WSi; a n + source and a n + drain region in said structure defined by selective donor ion implantation into said structure next to said first gate electrode; a p + source and a p + drain region in said structure defined by selective acceptor ion implantation into said structure next to said second gate electrode; first and second n-ohmic contacts alloyed to said n-source and n-drain regions, respectively; and, third and fourth p-ohmic contacts alloyed to said p-source and p-drain regions, respectively.

Claim 15

A low-power planar complementary GaAs based heterostructure integrated circuit structure comprising: semi-insulating GaAs substrate means having a flat major surface; planar epitaxial grown intrinsic layers sequentially grown in order over said flat major surface comprising a first epitaxially grown layer of intrinsic GaAs grown directly over said surface, said GaAs layer having high mobility and having a first bandgap; a second epitaxially grown layer of intrinsic (Al,Ga)As grown directly over said first layer, which i-(Al,Ga)As has a larger bandgap than said first bandgap, and in which the energy gap difference is divided between valence and conduction bands; a heavily doped In y Ga 1-y As (where 0<y<0.2) thin layer epitaxially grown on the final layer of said intrinsic layers and defining the location of a first gate electrode; a first metal gate electrode deposited on said In y Ga 1- As; a second metal gate electrode deposited on the surface of the final layer of said intrinsic layers, in which said first and second metal gate electrodes are of WSi; a n + source and a n + drain region in said structure defined by selective donor ion implantation into said structure next to said first gate electrode; a p + source and a p + drain region in said structure defined by selective acceptor ion implantation into said structure next to said second gate electrode; first and second n-ohmic contacts alloyed to said n-source and n-drain regions, respectively; and, third and fourth p-ohmic contacts alloyed to said p-source and p-drain regions, respectively.

Claim 16

A low-power planar complementary GaAs based heterostructure integrated circuit structure having complementary self-aligned gate (Al,Ga)As/GaAS heterostructure devices with an insulating (Al,Ga)As (SAG) gate structure to form CMOS-like GaAs IC's, the planar complementary IC structure comprising: semi-insulating GaAs substrate means having a flat major surface; a first MBE grown layer of intrinsic GaAs grown directly over said surface, said GaAs layer having high mobility and having a first bandgap; a second MBE grown layer of intrinsic (Al,Ga)As grown directly over said layer of i-GaAs, which i-(Al,Ga)As has a larger bandgap than said first bandgap, and in which th energy gap difference is divided between valence and conduction bands; a MBE grown thin-layer of heavily doped In y Ga 1-y As (where 0<y<0.2) on the layer of i-(Al,Ga)As and defining the location of a first gate electrode in which said heavily doped epitaxial layer of In y Ga 1-y As is of a thickness in the range of 200 to 500 Å; a first metal gate electrode deposited on the surface of the In y Ga 1-y As; a second metal gate electrode deposited on the surface of said i-(Al,Ga)As layer; a n + source and a n + drain region defined by selective donor ion implantation in said structure next to said first gate electrode; a p + source and a p + drain region defined by selective acceptor ion implantation in said structure next to said second gate electrode; first and second n-ohmic contacts alloyed to said n-source and n-drain regions, respectively; and, third and fourth p-ohmic contacts alloyed to said p-source and p-drain regions, respectively.

Claim 17

A low-power planar complementary GaAs based heterostructure integrated circuit structure having complementary self-aligned gate (Al,Ga)As/GaAS heterostructure devices with an insulating (Al,Ga)As (SAG) gate structure to form CMOS-like GaAs IC's, the planar complementary IC structure comprising: semi-insulating GaAs substrate means having a flat major surface; a first MBE grown layer of intrinsic GaAs grown directly over said surface, said GaAs layer having high mobility and having a first bandgap; a second MBE grown layer of intrinsic (Al,Ga)As grown directly over said layer of i-GaAs, which i-(Al,Ga)As has a larger bandgap than said first bandgap, and in which th energy gap difference is divided between valence and conduction bands; a MBE grown thin-layer of heavily doped In y Ga 1-y As (where 0<y<0.2) on the layer of i-(Al,Ga)As and defining the location of a first gate electrode in which said heavily doped epitaxial layer of In y Ga 1-y As is of a thickness in the range of 200 to 500 Å; a first metal gate electrode deposited on the surface of the In y Ga 1-y As; a second metal gate electrode deposited on the surface of said i-(Al,Ga)As layer; a n + source and a n + drain region defined by selective donor ion implantation in said structure next to said first gate electrode; a p + source and a p + drain region defined by selective acceptor ion implantation in said structure next to said second gate electrode; first and second n-ohmic contacts alloyed to said n-source and n-drain regions, respectively; and, third and fourth p-ohmic contacts alloyed to said p-source and p-drain regions, respectively.

Claim 18

A low-power planar complementary GaAs based heterostructure integrated circuit structure having complementary self-alinged gate (Al,Ga)As/GaAs heterostructure devices with an insulating (Al,Ga)As (SAG) gate structure to form CMOS-like GaAs IC's, the planar complementary IC structure comprising: semi-insulating GaAs substrate means having a flat major surface; a first MBE grown layer of intrinsic GaAs grown directly over said surface, said GaAs layer having high mobility and having a first bandgap; a second MBE grown layer of intrinsic (Al,Ga)As grown directly over said layer of i-GaAs, which i-(Al,Ga)As has a larger bandgap than said first bandgap, and in which the energy gap difference is divided between valence and conduction bands; a MBE grown thin-layer of heavily doped In y Ga 1-y As (where y is a fraction on the order of 0.15) on the layer of i-(Al,Ga)As and defining the location of a first gate electrode; a first metal gate electrode deposited on the surface of the In y Ga 1-y As; a second metal gate electrode deposited on the surface of said i-(Al,Ga)As layer; a n + and a n + drain region defined by selective donor ion implantation in said structure next to said first gate electrode; a p + source and a p + drain region defined by selective acceptor ion implantation in said structure next to said second gate electrode; first and second n-ohmic contacts alloyed to said n-source and n-drain regions, respectively; and, third and fourth p-ohmic contacts alloyed to said p-source and p-drain regions, respectively.

Claim 19

A low-power planar complementary GaAs based heterostructure integrated circuit structure having complementary self-alinged gate (Al,Ga)As/GaAs heterostructure devices with an insulating (Al,Ga)As (SAG) gate structure to form CMOS-like GaAs IC's, the planar complementary IC structure comprising: semi-insulating GaAs substrate means having a flat major surface; a first MBE grown layer of intrinsic GaAs grown directly over said surface, said GaAs layer having high mobility and having a first bandgap; a second MBE grown layer of intrinsic (Al,Ga)As grown directly over said layer of i-GaAs, which i-(Al,Ga)As has a larger bandgap than said first bandgap, and in which the energy gap difference is divided between valence and conduction bands; a MBE grown thin-layer of heavily doped In y Ga 1-y As (where y is a fraction on the order of 0.15) on the layer of i-(Al,Ga)As and defining the location of a first gate electrode; a first metal gate electrode deposited on the surface of the In y Ga 1-y As; a second metal gate electrode deposited on the surface of said i-(Al,Ga)As layer; a n + and a n + drain region defined by selective donor ion implantation in said structure next to said first gate electrode; a p + source and a p + drain region defined by selective acceptor ion implantation in said structure next to said second gate electrode; first and second n-ohmic contacts alloyed to said n-source and n-drain regions, respectively; and, third and fourth p-ohmic contacts alloyed to said p-source and p-drain regions, respectively.

Claim 20

A low-power planar complementary GaAs based heterostructure integrated circuit structure having complementary self-aligned gate (Al,Ga)As/GaAs heterostructure devices with an insulating (Al,Ga)As (SAG) gate structure to form CMOS-like GaAs IC's, the planar complementary IC structure comprising: semi-insulating GaAs substrate means having a flat major surface; a first MBE grown layer of intrinsic GaAs grown directly over said surface, said GaAs layer having high mobility and having a first bandgap; a second MBE grown layer of intrinsic (Al,Ga)As grown directly over said layer of i-GaAs, which i-(Al,Ga)As has a larger bandgap than said first bandgap, and in which the energy gap difference is divided between valence and conduction bands; a MBE grown thin-layer of heavily doped IN y Ga 1-y As (where 0<y<0.2) on the layer of i-(Al,Ga)As and defining the location of a first gate electrode; a first metal gate electrode deposited on the surface of the In y Ga 1-y As; a second metal gate electrode deposited on the surface of said i-(Al,Ga)As layer, in which said first and second metal gate electrodes are of WSi; a n + source and a n + drain region defined by selective donor ion implantation in said structure next to said first gate electrode; a p + source and a p + drain region defined by selective acceptor ion implantation in said structure next to said second gate electrode; first and second n-ohmic contacts alloyed to said n-source and n-drain regions, respectively; and, third and fourth p-ohmic contacts alloyed to said p-source and p-drain regions, respectively.

Claim 21

A low-power planar complementary GaAs based heterostructure integrated circuit structure having complementary self-aligned gate (Al,Ga)As/GaAs heterostructure devices with an insulating (Al,Ga)As (SAG) gate structure to form CMOS-like GaAs IC's, the planar complementary IC structure comprising: semi-insulating GaAs substrate means having a flat major surface; a first MBE grown layer of intrinsic GaAs grown directly over said surface, said GaAs layer having high mobility and having a first bandgap; a second MBE grown layer of intrinsic (Al,Ga)As grown directly over said layer of i-GaAs, which i-(Al,Ga)As has a larger bandgap than said first bandgap, and in which the energy gap difference is divided between valence and conduction bands; a MBE grown thin-layer of heavily doped IN y Ga 1-y As (where 0<y<0.2) on the layer of i-(Al,Ga)As and defining the location of a first gate electrode; a first metal gate electrode deposited on the surface of the In y Ga 1-y As; a second metal gate electrode deposited on the surface of said i-(Al,Ga)As layer, in which said first and second metal gate electrodes are of WSi; a n + source and a n + drain region defined by selective donor ion implantation in said structure next to said first gate electrode; a p + source and a p + drain region defined by selective acceptor ion implantation in said structure next to said second gate electrode; first and second n-ohmic contacts alloyed to said n-source and n-drain regions, respectively; and, third and fourth p-ohmic contacts alloyed to said p-source and p-drain regions, respectively.

Claim 22

A complementary, planar heterostructure IC in which both the n-channel and p-channel transistors utilize a 2D electron (hole) gas in an undoped high mobility channel to form CMOS-like IC's, the complementary, planar IC structure comprising: semi-insulating GaAs substrate means having a flat major surface; a first epitaxially grown layer of intrinsic GaAs over said surface, said GaAs layer having high mobility and having a first bandgap; a second eptixially grown layer of intrinsic (Al,Ga)As over said first layer, which i-(Al,Ga)As has a larger bandgap than said first bandgap, and in which the energy gap difference is divided between valence and conduction bands; a third epitaxially grown layer of intrinsic GaAs over said second layer; a fourth epitaxially grown area of highly doped In y Ga 1-y As on said third layer and defining the location of a first gate electrode, in which said highly doped layer of In y Ga 1-y As is of a thickness of less than about 1000 Å; a first metal gate electrode deposited on said In y Ga 1-y As; a second metal gate electrode deposited on the surface of said third epitaxially layer; a n + and a n + drain region defined by selective donor ion implantation in said structure next to said first gate electrode; a p + source and a p + drain region defined by selective acceptor ion implantation in said structure next to said second gate electrode; first and second n-ohmic contacts alloyed to said n-source and n-drain regions, respectively; and, third and fourth p-ohmic contacts alloyed to said p-source and p-drain regions, respectively.

Claim 23

A complementary, planar heterostructure IC in which both the n-channel and p-channel transistors utilize a 2D electron (hole) gas in an undoped high mobility channel to form CMOS-like IC's, the complementary, planar IC structure comprising: semi-insulating GaAs substrate means having a flat major surface; a first epitaxially grown layer of intrinsic GaAs over said surface, said GaAs layer having high mobility and having a first bandgap; a second eptixially grown layer of intrinsic (Al,Ga)As over said first layer, which i-(Al,Ga)As has a larger bandgap than said first bandgap, and in which the energy gap difference is divided between valence and conduction bands; a third epitaxially grown layer of intrinsic GaAs over said second layer; a fourth epitaxially grown area of highly doped In y Ga 1-y As on said third layer and defining the location of a first gate electrode, in which said highly doped layer of In y Ga 1-y As is of a thickness of less than about 1000 Å; a first metal gate electrode deposited on said In y Ga 1-y As; a second metal gate electrode deposited on the surface of said third epitaxially layer; a n + and a n + drain region defined by selective donor ion implantation in said structure next to said first gate electrode; a p + source and a p + drain region defined by selective acceptor ion implantation in said structure next to said second gate electrode; first and second n-ohmic contacts alloyed to said n-source and n-drain regions, respectively; and, third and fourth p-ohmic contacts alloyed to said p-source and p-drain regions, respectively.

Claim 24

A complementary, planar heterostructure IC in which both the n-channel and p-channel transistors utilize a 2D electron (hole) gas in an undoped high mobility channel to form CMOS-like IC's, the complementary, planar IC structure comprising: semi-insulating GaAs substrate means having a flat major surface; a first epitaxially grown layer of intrinsic GaAs over said surface, said GaAs layer having high mobility and having a first bandgap; a second epitaxially grown layer of intrinsic (Al,Ga)As over said first layer, which i-(Al,Ga)As has a larger bandgap than said first bandgap, and in which the energy gap difference is divided between valence and conduction bands; a third epitaxially grown layer of intrinsic GaAs over said second layer; a fourth epitaxially grown area of highly doped In y Ga 1-y As on said third layer and defining the location of a first gate electrode, in which y is a fraction on the order of 0.15; a first metal gate electrode deposited on said In y Ga 1-y As; a second metal gate electrode deposited on the surface of said third epitaxially layer; a n + source and a n + drain region defined by selective donor ion implantation in said structure next to said first gate electrode; a p + source and a p + drain region defined by selective acceptor ion implantation in said structure next to said second gate electrode; first and second n-ohmic contacts alloyed to said n-source and n-drain regions, respectively; and, third and fourth p-ohmic contacts alloyed to said p-source and p-drain regions, respectively.

Claim 25

A complementary, planar heterostructure IC in which both the n-channel and p-channel transistors utilize a 2D electron (hole) gas in an undoped high mobility channel to form CMOS-like IC's, the complementary, planar IC structure comprising: semi-insulating GaAs substrate means having a flat major surface; a first epitaxially grown layer of intrinsic GaAs over said surface, said GaAs layer having high mobility and having a first bandgap; a second epitaxially grown layer of intrinsic (Al,Ga)As over said first layer, which i-(Al,Ga)As has a larger bandgap than said first bandgap, and in which the energy gap difference is divided between valence and conduction bands; a third epitaxially grown layer of intrinsic GaAs over said second layer; a fourth epitaxially grown area of highly doped In y Ga 1-y As on said third layer and defining the location of a first gate electrode, in which y is a fraction on the order of 0.15; a first metal gate electrode deposited on said In y Ga 1-y As; a second metal gate electrode deposited on the surface of said third epitaxially layer; a n + source and a n + drain region defined by selective donor ion implantation in said structure next to said first gate electrode; a p + source and a p + drain region defined by selective acceptor ion implantation in said structure next to said second gate electrode; first and second n-ohmic contacts alloyed to said n-source and n-drain regions, respectively; and, third and fourth p-ohmic contacts alloyed to said p-source and p-drain regions, respectively.

Claim 26

A complementary, planar heterostructure IC in which both the n-channel and p-channel transistors utilize a 2D electron (hole) gas in an undoped high mobility channel to form CMOS-like IC's, the complementary, planar IC structure comprising: semi-insulating GaAs substrate means having a flat major surface; a first epitaxially grown layer of intrinsic GaAs over said surface, said GaAs layer having high mobility and having a first bandgap; a second epitaxially grown layer of intrinsic (Al,Ga)As over said first layer, which i-(Al,Ga)As has a larger bandgap than said first bandgap, and in which the energy gap difference is divided between valence and conduction bands; a third epitaxially grown layer of intrinsic GaAS over said second layer; a fourth epitaxially grown area of highly doped In y Ga 1-y As on said third layer and defining the location of a first gate electrode; a first metal gate electrode deposited on said In y Ga 1-y As; a second metal gate electrode deposited on the surface of said third epitaxial layer, in which said first and second metal gate electrodes are of WSi; a n + source and a n + drain region defined by selective donor ion implantation in said structure next to said first gate electrode; a p + source and a p + drain region defined by selective acceptor ion implantation in said structure next to said second gate electrode; first and second n-ohmic contacts alloyed to said n-source and n-drain regions, respectively; and, third and fourth p-ohmic contacts alloyed to said p-source and p-drain regions, respectively.

Claim 27

A complementary, planar heterostructure IC in which both the n-channel and p-channel transistors utilize a 2D electron (hole) gas in an undoped high mobility channel to form CMOS-like IC's, the complementary, planar IC structure comprising: semi-insulating GaAs substrate means having a flat major surface; a first epitaxially grown layer of intrinsic GaAs over said surface, said GaAs layer having high mobility and having a first bandgap; a second epitaxially grown layer of intrinsic (Al,Ga)As over said first layer, which i-(Al,Ga)As has a larger bandgap than said first bandgap, and in which the energy gap difference is divided between valence and conduction bands; a third epitaxially grown layer of intrinsic GaAS over said second layer; a fourth epitaxially grown area of highly doped In y Ga 1-y As on said third layer and defining the location of a first gate electrode; a first metal gate electrode deposited on said In y Ga 1-y As; a second metal gate electrode deposited on the surface of said third epitaxial layer, in which said first and second metal gate electrodes are of WSi; a n + source and a n + drain region defined by selective donor ion implantation in said structure next to said first gate electrode; a p + source and a p + drain region defined by selective acceptor ion implantation in said structure next to said second gate electrode; first and second n-ohmic contacts alloyed to said n-source and n-drain regions, respectively; and, third and fourth p-ohmic contacts alloyed to said p-source and p-drain regions, respectively.