EP0165798A1
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EP
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Semiconductor device comprising N-channel and P-channel transistors and production method
Assignee: Fujitsu Ltd
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Filing: 1985-06-17
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Granted: —
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Expires: 2005-06-17
Abstract
Abstract A semiconductor device complementary circuit comprises an n-channel transistor (ON) using a two-dimensional electron gas (27) and a p-channel transistor (Qp) using a two-dimensional hole gas (28). The device comprises: a semi-insulating GaAs substrate (11); a channel layer (12) of i-type GaAs having n - -type source and drain regions (18 and 19) and p + -type source and drain regions (20 and 21); a buffer layer (13) of i-type AlGaAs preventing carriers from passing through it; and, first and second control layers (14 and 15) of GaAs and/or AlGaAs having n-type or p-type conductivity. These layers are epitaxially formed in sequence on the substrate (11) by an MBE method or an MOCVD method. Metal electrodes (16, 17, 23 to 26) are formed on the first and second control layers (14 and 15), n + -type regions (18 and 19) and p"-type regions (20 and 21).
Inventors
- 👤 Takashi Mimura
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-06 15:23
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/40; H10D30/47; H10D30/471; H10D30/475; H10D64/00; H10D64/60; H10D64/602; H10D84/00; H10D84/01; H10D84/02; H10D84/05
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
219 words
A semiconductor device comprising an n-channel transistor (Q N ) and a p-channel transistor (Qp), including in combination: (a) a semi-insulating single crystalline substrate (11); (b) a channel layer (12) of an undoped single crystalline semiconductor formed on the substrate (11), and having a pair of n +- type impurity regions (18, 19) sandwiching an n-channel region (27) forming a two-dimensional electron gas layer for the n-channel transistor (Q N ) and a pair of p +- type impurity regions (20, 21) sandwiching a p-channel region (28) forming a two-dimensional hole gas layer for the p-channel transistor (Qp); (c) a buffer layer (13) of an undoped single crystalline semiconductor having an energy gap larger than that of the channel- layer (12) and formed on the n-channel (27) and p-channel (28) regions of the channel layer (12); (d) a first control layer (14) of a doped single crystalline semiconductor formed on the buffer layer (13) above the n-channel region (27); (e) a second control layer (15) of a doped single crystalline semiconductor layer formed on the buffer layer (13) above the p-channel region (28); and, (f) electrodes (16, 17, 23, 24, 25, 26) formed on the first (14) and second (15) control layers, the n +- type impurity regions (18, 19), and the p + -type impurity regions (20, 21).
Claim 2
Dependent Claim
219 words
A semiconductor device comprising an n-channel transistor (Q N ) and a p-channel transistor (Qp), including in combination: (a) a semi-insulating single crystalline substrate (11); (b) a channel layer (12) of an undoped single crystalline semiconductor formed on the substrate (11), and having a pair of n +- type impurity regions (18, 19) sandwiching an n-channel region (27) forming a two-dimensional electron gas layer for the n-channel transistor (Q N ) and a pair of p +- type impurity regions (20, 21) sandwiching a p-channel region (28) forming a two-dimensional hole gas layer for the p-channel transistor (Qp); (c) a buffer layer (13) of an undoped single crystalline semiconductor having an energy gap larger than that of the channel- layer (12) and formed on the n-channel (27) and p-channel (28) regions of the channel layer (12); (d) a first control layer (14) of a doped single crystalline semiconductor formed on the buffer layer (13) above the n-channel region (27); (e) a second control layer (15) of a doped single crystalline semiconductor layer formed on the buffer layer (13) above the p-channel region (28); and, (f) electrodes (16, 17, 23, 24, 25, 26) formed on the first (14) and second (15) control layers, the n +- type impurity regions (18, 19), and the p + -type impurity regions (20, 21).
Claim 3
Dependent Claim
26 words
A semiconductor device according to claim 1, wherein the substrate (11) is GaAs, the channel layer (12) is GaAs and the buffer layer (13) is AlGaAs.
Claim 4
Dependent Claim
22 words
A semiconductor device according to claim 1 or 2, wherein the first (14) and/or second (15) control layer is GaAs or AlGaAs.
Claim 5
Dependent Claim
22 words
A semiconductor device according to claim 3, wherein the first (14) and/or second (15) control layer contains donor impurities or acceptor impurities.
Claim 6
Dependent Claim
29 words
A semiconductor device according to any one of the preceding claims, wherein the first control layer (14) and the second control layer (15) are formed of the same material.
Claim 7
Dependent Claim
164 words
A method of producing a semiconductor device according to claim 1, comprising the steps of: epitaxially forming a channel layer (12) of undoped single crystalline semiconductor on a semi-insulating single crystalline substrate (11); epitaxially forming a buffer layer (13) of undoped single crystalline semiconductor on the channel layer (12); epitaxially and selectively forming a first control layer (14) of a doped single crystalline semiconductor on the buffer layer (13); epitaxially and selectively forming a second control layer (15) of a doped single crystalline semiconductor on the buffer layer (13); forming a first control electrode (16) and a second control electrode (17) on the first control layer (14) and the second control layer (15) respectively; forming a pair of impurity regions (18, 19) of first conductivity type in the channel layer (12); forming a pair of impurity regions (20, 21) of second conductivity type, opposite the first conductivity type, in the channel layer (12); and, forming electrodes on the impurity regions (18, 19, 20, 21).
Claim 8
Dependent Claim
39 words
A method according to claim 6, wherein the channel layer (12), the buffer layer (13), the first control layer (14), and the second control layer (15) are all formed by molecular beam epitaxy or metal organic chemical vapour deposition.
Claim 9
Dependent Claim
26 words
A method according to claim 6 or 7, wherein the channel layer (12) is made of GaAs and the buffer layer (13) is made of AlGaAs.
Claim 10
Dependent Claim
27 words
A method according to claim 6, 7 or 8, wherein the first control layer (14) and the second control layer (15) are made from GaAs and/or AlGaAs.
Claim 11
Dependent Claim
41 words
A method according to claim 6, 7, 8, or 9, wherein the step of forming the first control layer (14) and the step of forming the second control layer (15) are carried out simultaneously using the same doped single crystalline semiconductor.
References Cited (Backward Citations)
EP0033037A2
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EP0055968A2
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