US5592018A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Membrane dielectric isolation IC fabrication
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
•
Filing: 1995-06-07
•
Granted: 1997-01-07
•
Expires: 2015-06-07
Abstract
Abstract General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.
Inventors
- 👤 Glenn J. Leedy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 05:49
CPC Classifications
H; H10; H10W; H10W90/00; H10P; H10P95/00; G; G03; G03F; G03F7/00; G03F7/70; G03F7/70483; G03F7/70605; G03F7/70653; G03F7/70658; G11; G11C; G11C29/00; G11C29/006; H10P90/00; H10P90/19; H10P90/1904; H10P90/1906; H10W10/00; H10W10/01; H10W10/011; H10W10/021; H10W10/061; H10W10/10; H10W10/181; H10W10/20; H10W70/00; H10W70/60; H10W70/611; H10W70/62; H10W70/65; H10W70/67; H10W70/68; H10W70/685; H10W70/688; G02; G02F; G02F1/00; G02F1/01; G02F1/13; G02F1/133; G02F1/1333; G02F1/1345; G02F1/13452; G02F1/136; G02F1/1362; G02F1/136277; G02F1/136281; H10D; H10D84/00; H10D84/01; H10D84/02; H10D84/03; H10D84/038; H10D88/00; H10D88/01; H10D89/00; H10D89/10; H10W70/682; H10W72/00; H10W72/20; H10W72/221; H10W72/29; H10W72/90; H10W72/941; H10W72/942; H10W90/701; H10W90/721; H10W90/724; Y; Y10; Y10S; Y10S148/00; Y10S148/135; Y10S438/00; Y10S438/928; Y10S438/938; Y10S438/942; Y10S438/967; Y10S438/977; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49124; Y10T29/49128; Y10T29/49155; Y10T29/49162; Y10T29/49165; Y10T29/49169; Y10T29/49171; Y10T29/49204; Y10T29/49208; Y10T29/4921
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
103 words
A dielectrically isolated integrated circuit formed by a method comprising the steps of: providing a substrate having a principal surface; forming an etch barrier layer in the substrate parallel to the principal surface; forming the integrated circuit on the principal surface wherein the integrated circuit includes at least one transistor; depositing a low stress insulating membrane over the integrated circuit; and etching away to the etch barrier layer a portion of the substrate from a backside of the substrate opposite the integrated circuit; wherein the insulating membrane and remaining substrate containing the integrated circuit have a combined thickness less than about 50 μm.
Claim 2
Dependent Claim
103 words
A dielectrically isolated integrated circuit formed by a method comprising the steps of: providing a substrate having a principal surface; forming an etch barrier layer in the substrate parallel to the principal surface; forming the integrated circuit on the principal surface wherein the integrated circuit includes at least one transistor; depositing a low stress insulating membrane over the integrated circuit; and etching away to the etch barrier layer a portion of the substrate from a backside of the substrate opposite the integrated circuit; wherein the insulating membrane and remaining substrate containing the integrated circuit have a combined thickness less than about 50 μm.
Claim 3
Dependent Claim
31 words
The integrated circuit of claim 1, wherein the method further comprises the steps of: forming an epitaxial layer on the principal surface; and forming the integrated circuit in the epitaxial layer.
Claim 4
Dependent Claim
22 words
The integrated circuit of claim 1 wherein the method further comprises the step of isolating the integrated circuit devices with dielectric material.
Claim 5
Dependent Claim
15 words
The integrated circuit of claim 3 wherein the devices are isolated by trench isolation techniques.
Claim 6
Dependent Claim
15 words
The integrated circuit of claim 3 wherein the devices are isolated by LOCOS isolation techniques.
Claim 7
Dependent Claim
26 words
The integrated circuit of claim 1, wherein the method further comprises the step of forming conductors in the insulating membrane for interconnecting the integrated circuit devices.
Claim 8
Dependent Claim
18 words
The integrated circuit of claim 1 wherein the method further comprises bonding a bonding frame to the substrate.
Claim 9
Dependent Claim
83 words
An integrated circuit comprising: a semiconductor substrate with a principal surface; a first plurality of semiconductor devices formed on the principal surface of the substrate wherein said first plurality of semiconductor devices includes at least one transistor; and an insulating membrane of dielectric material having a tensile surface stress level of 2 to 100 times less than the fracture strength of the dielectric material formed over the first plurality of semiconductor devices; wherein a thickness of the integrated circuit is between 2-50 μm.
Claim 10
Dependent Claim
83 words
An integrated circuit comprising: a semiconductor substrate with a principal surface; a first plurality of semiconductor devices formed on the principal surface of the substrate wherein said first plurality of semiconductor devices includes at least one transistor; and an insulating membrane of dielectric material having a tensile surface stress level of 2 to 100 times less than the fracture strength of the dielectric material formed over the first plurality of semiconductor devices; wherein a thickness of the integrated circuit is between 2-50 μm.
Claim 11
Dependent Claim
15 words
The integrated circuit of claim 8 further comprising a bonding frame coupled to the substrate.
Claim 12
Dependent Claim
23 words
The integrated circuit of claim 8 further comprising a second plurality of semiconductor devices formed on a backside surface of the semiconductor substrate.
Claim 13
Dependent Claim
19 words
The integrated circuit of claim 8 wherein the substrate has a tensile stress of 10 8 dynes/cm 2 .
Claim 14
Dependent Claim
45 words
An integrated circuit comprising: a semiconductor substrate having a surface tension of approximately 10 8 dynes/cm 2 ; and a plurality of semiconductor devices formed on a principal surface of the substrate, wherein a thickness of the integrated circuit is less than about 50 μm.
Claim 15
Dependent Claim
45 words
An integrated circuit comprising: a semiconductor substrate having a surface tension of approximately 10 8 dynes/cm 2 ; and a plurality of semiconductor devices formed on a principal surface of the substrate, wherein a thickness of the integrated circuit is less than about 50 μm.
Claim 16
Dependent Claim
15 words
The integrated circuit of claim 12 wherein the devices are electrically isolated by dielectric material.
References Cited (Backward Citations)
US34893A
Cited
US4070230A
Cited
US4131985A
Cited
US4618397A
Cited
US4702936A
Cited
US4952446A
Cited
US4721938A
Cited
USRE34893E
Cited
US5110373A
Cited
US5071510A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-01-07 | 2000-07-08 | 2001-01-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-01-07 | 2004-07-08 | 2005-01-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-01-07 | 2008-07-08 | 2009-01-07 | $7700.00 | Window Closed / Lapsed |