US6996009B2 — NOR flash memory cell with high storage density

Claim 1

Independent Claim 130 words

A NOR flash memory cell, comprising: a vertical floating gate transistor extending outwardly from a substrate, the floating gate transistor having a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, a floating gate separated from the channel region by a gate insulator, and a control gate separated from the floating gate by a gate dielectric; a sourceline formed in a trench adjacent to the vertical floating gate transistor, wherein the first source/drain region is coupled to the sourceline; a transmission line coupled to the second source/drain region; and wherein the floating gate transistor is a programmed floating gate transistor having a charge trapped in the floating gate such that the programmed floating gate transistor operates at reduced drain source current.

Claim 2

Dependent Claim 130 words

A NOR flash memory cell, comprising: a vertical floating gate transistor extending outwardly from a substrate, the floating gate transistor having a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, a floating gate separated from the channel region by a gate insulator, and a control gate separated from the floating gate by a gate dielectric; a sourceline formed in a trench adjacent to the vertical floating gate transistor, wherein the first source/drain region is coupled to the sourceline; a transmission line coupled to the second source/drain region; and wherein the floating gate transistor is a programmed floating gate transistor having a charge trapped in the floating gate such that the programmed floating gate transistor operates at reduced drain source current.

Claim 3

Dependent Claim 37 words

The NOR flash memory cell of claim 1 , wherein the first source/drain region of the floating gate transistor includes a source region and the second source/drain region of the floating gate transistor includes a drain region.

Claim 4

Dependent Claim 17 words

The NOR flash memory cell of claim 1 , wherein the transmission line includes a bit line.

Claim 5

Dependent Claim 21 words

The NOR flash memory cell of claim 1 , wherein the gate insulator has a thickness of approximately 10 nanometers (nm).

Claim 6

Dependent Claim 122 words

A NOR flash memory cell, comprising: a vertical floating gate transistor formed according to a modified DRAM fabrication process, the floating gate transistor having a source region, a drain region, a channel region between the source and the drain regions, a floating gate separated from the channel region by a gate insulator, and a control gate separated from the floating gate by a gate dielectric; a wordline coupled to the control gate; a sourceline formed in a trench adjacent to the vertical floating gate transistor, wherein the source region is coupled to the sourceline; a bit line coupled to the drain region; and wherein the floating gate transistor is a programmed floating gate transistor having a charge trapped in the floating gate.

Claim 7

Dependent Claim 122 words

A NOR flash memory cell, comprising: a vertical floating gate transistor formed according to a modified DRAM fabrication process, the floating gate transistor having a source region, a drain region, a channel region between the source and the drain regions, a floating gate separated from the channel region by a gate insulator, and a control gate separated from the floating gate by a gate dielectric; a wordline coupled to the control gate; a sourceline formed in a trench adjacent to the vertical floating gate transistor, wherein the source region is coupled to the sourceline; a bit line coupled to the drain region; and wherein the floating gate transistor is a programmed floating gate transistor having a charge trapped in the floating gate.

Claim 8

Dependent Claim 22 words

The NOR flash memory cell of claim 5 , wherein the gate insulator has a thickness of at least 10 nanometers (nm).

Claim 9

Dependent Claim 173 words

A NOR memory array, comprising: a number of NOR flash memory cells extending from a substrate and separated by trenches, wherein each flash memory cell includes a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, a floating gate separated from the channel by a first gate insulator, and a control gate separated from the floating gate by a second gate insulator; a number of bit lines coupled to the second source/drain region of each flash memory cell along rows of the memory array; a number of word lines coupled to the control gate of each flash memory cell along columns of the memory array; a number of sourcelines along rows in the trenches between the number of flash memory cells extending from a substrate, wherein the first source/drain region of each flash memory cell is coupled to the number of sourcelines; and wherein at least one of the flash memory cells is a programmed cell having a charge trapped in the floating gate.

Claim 10

Dependent Claim 173 words

A NOR memory array, comprising: a number of NOR flash memory cells extending from a substrate and separated by trenches, wherein each flash memory cell includes a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, a floating gate separated from the channel by a first gate insulator, and a control gate separated from the floating gate by a second gate insulator; a number of bit lines coupled to the second source/drain region of each flash memory cell along rows of the memory array; a number of word lines coupled to the control gate of each flash memory cell along columns of the memory array; a number of sourcelines along rows in the trenches between the number of flash memory cells extending from a substrate, wherein the first source/drain region of each flash memory cell is coupled to the number of sourcelines; and wherein at least one of the flash memory cells is a programmed cell having a charge trapped in the floating gate.

Claim 11

Dependent Claim 20 words

The memory array of claim 7 , wherein each NOR flash memory cell includes a vertical NOR flash memory cell.

Claim 12

Dependent Claim 26 words

The memory array of claim 7 , wherein the first gate insulator of each NOR flash memory cell has a thickness of approximately 10 nanometers (nm).

Claim 13

Dependent Claim 38 words

The memory array of claim 7 , wherein the number of NOR flash memory cells extending from a substrate operate as equivalent to a transistor having a size of approximately 2.0 lithographic features squared (2 F 2 ).

Claim 14

Dependent Claim 237 words

A NOR memory array, comprising: a number of vertical pillars formed in rows and columns extending outwardly from a substrate and separated by a number of trenches, wherein the number of vertical pillars serve as floating gate transistors including a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, a floating gate separated from the channel by a first gate insulator in the trenches along rows of pillars, and a control gate separated from the floating gate by a second gate insulator, wherein along columns of the pillars adjacent pillars include a floating gate transistor which operates as a programmed cell on one side of a trench and a floating gate transistor which operates as a reference cell having a programmed conductivity state on the opposite side of the trench; a number of bit lines coupled to the second source/drain region of each transistor along rows of the memory array; a number of word lines coupled to the control gate of each floating gate transistor along columns of the memory array; a number of sourcelines formed in a bottom of the trenches between rows of the pillars and coupled to the first source/drain regions of each floating gate transistor along rows of pillars, wherein along columns of the pillars the first source/drain region of each transistor in column adjacent pillars couples to the sourceline in a shared trench.

Claim 15

Dependent Claim 237 words

A NOR memory array, comprising: a number of vertical pillars formed in rows and columns extending outwardly from a substrate and separated by a number of trenches, wherein the number of vertical pillars serve as floating gate transistors including a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, a floating gate separated from the channel by a first gate insulator in the trenches along rows of pillars, and a control gate separated from the floating gate by a second gate insulator, wherein along columns of the pillars adjacent pillars include a floating gate transistor which operates as a programmed cell on one side of a trench and a floating gate transistor which operates as a reference cell having a programmed conductivity state on the opposite side of the trench; a number of bit lines coupled to the second source/drain region of each transistor along rows of the memory array; a number of word lines coupled to the control gate of each floating gate transistor along columns of the memory array; a number of sourcelines formed in a bottom of the trenches between rows of the pillars and coupled to the first source/drain regions of each floating gate transistor along rows of pillars, wherein along columns of the pillars the first source/drain region of each transistor in column adjacent pillars couples to the sourceline in a shared trench.

Claim 16

Dependent Claim 51 words

The memory array of claim 11 , wherein each floating gate is a vertical floating gate formed in a trench below a top surface of each pillar such that each trench houses a pair of floating gates on opposing sides of the trench opposing the channel regions in column adjacent pillars.

Claim 17

Dependent Claim 61 words

The memory array of claim 12 , wherein the control gate is formed in the trench below the top surface of the pillars and between the pair of floating gates, wherein each pair of floating gates shares a single control gate, and wherein each floating gate includes a vertically oriented floating gate having a vertical length of less than 100 nanometers.

Claim 18

Dependent Claim 65 words

The memory array of claim 12 , wherein the control gates are formed in the trench below the top surface of the pillars and between the pair of floating gates such that each trench houses a pair of control gates each addressing a floating gate on opposing sides of the trench respectively, and wherein the pair of control gates are separated by an insulator layer.

Claim 19

Dependent Claim 31 words

The memory array of claim 12 , wherein the control gates are disposed vertically above the floating gates, and wherein each pair of floating gates shares a single control gate line.

Claim 20

Dependent Claim 20 words

The memory array of claim 12 , wherein a pair of control gates are disposed vertically above the floating gates.

Claim 21

Dependent Claim 73 words

The memory array of claim 11 , wherein each floating gate is a horizontally oriented floating gate formed in a trench below a top surface of each pillar such that each trench houses a floating gate opposing the channel regions in column adjacent pillars on opposing sides of the trench, and wherein each horizontally oriented floating gate has a vertical length of less than 100 nanometers opposing the channel regions of the pillars.

Claim 22

Dependent Claim 18 words

The memory array of claim 17 , wherein the control gates are disposed vertically above the floating gates.

Claim 23

Dependent Claim 35 words

The memory array of claim 11 , wherein the number of sourcelines formed in a bottom of the trenches between rows of the pillars include a doped region implanted in the bottom of the trench.

Claim 24

Dependent Claim 25 words

The memory array of claim 11 , wherein the first gate insulator of each floating gate transistor has a thickness of approximately 10 nanometers (nm).

Claim 25

Dependent Claim 31 words

The memory array of claim 11 , wherein each floating gate transistor operates as equivalent to a transistor having a size of approximately 2.0 lithographic features squared (2 F 2 ).

Claim 26

Dependent Claim 192 words

A memory device, comprising: a NOR memory array, wherein the memory array includes a number of vertical NOR flash cells extending outwardly from a substrate and separated by trenches, wherein each NOR flash cell includes a source region, a drain region, a channel region between the source and the drain regions, a floating gate separated from the channel region by a first gate insulator, and a control gate separated from the floating gate by a second gate insulator; a number of bitlines coupled to the drain region of each vertical NOR flash cell along rows of the memory array; a number of wordlines coupled to the control gate of each vertical NOR flash cell along columns of the memory array; a number of sourcelines, wherein the first source/drain region of each vertical NOR flash cell is integrally formed with the number of sourcelines along rows in the trenches between the number of vertical NOR flash cells extending from a substrate; a wordline address decoder coupled to the number of wordlines; a bitline address decoder coupled to the number of bitlines; and one or more sense amplifiers coupled to the number of bitlines.

Claim 27

Dependent Claim 192 words

A memory device, comprising: a NOR memory array, wherein the memory array includes a number of vertical NOR flash cells extending outwardly from a substrate and separated by trenches, wherein each NOR flash cell includes a source region, a drain region, a channel region between the source and the drain regions, a floating gate separated from the channel region by a first gate insulator, and a control gate separated from the floating gate by a second gate insulator; a number of bitlines coupled to the drain region of each vertical NOR flash cell along rows of the memory array; a number of wordlines coupled to the control gate of each vertical NOR flash cell along columns of the memory array; a number of sourcelines, wherein the first source/drain region of each vertical NOR flash cell is integrally formed with the number of sourcelines along rows in the trenches between the number of vertical NOR flash cells extending from a substrate; a wordline address decoder coupled to the number of wordlines; a bitline address decoder coupled to the number of bitlines; and one or more sense amplifiers coupled to the number of bitlines.

Claim 28

Dependent Claim 25 words

The memory device of claim 22 , wherein the first gate insulator of each NOR flash cell has a thickness of approximately 10 nanometers (nm).

Claim 29

Dependent Claim 34 words

The memory device of claim 23 , wherein the wordline address decoder and the bitline address decoder each include conventionally fabricated MOSFET transistors having thin gate insulators formed of silicon dioxide (SiO 2 ).

Claim 30

Dependent Claim 30 words

The memory device of claim 23 , wherein the one or more sense amplifiers include conventionally fabricated MOSFET transistors having thin gate insulators formed of silicon dioxide (SiO 2 ).

Claim 31

Dependent Claim 285 words

An electronic system, comprising: a processor; and a memory device coupled to the processor, wherein the memory device includes a NOR memory array, the NOR memory array including; a number of vertical pillars formed in rows and columns extending outwardly from a substrate and separated by a number of trenches, wherein each vertical pillar comprises a pair of floating gate transistors on opposing sides of each pillar, including a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, a floating gate separated from the channel region by a first gate insulator in the trenches along rows of pillars, and a control gate separated from the floating gate by a second gate insulator, wherein along columns of the pillars the trench between column adjacent pillars include a pair of floating gates each one opposing the channel regions of the pillar on a respective side of the trench; a number of bit lines coupled to the second source/drain region of each floating gate transistor along rows of the memory array; a number of word lines coupled to the control gate of each floating gate transistor along columns of the memory array; a number of sourcelines formed in a bottom of the trenches between rows of the pillars and coupled to the first source/drain regions of each floating gate transistor along rows of pillars, wherein along rows of the pillars the first source/drain region of each floating gate transistor in column adjacent pillars couples to the sourceline in a shared trench such that each floating gate transistor neighboring the shared trench shares a common sourceline; and wherein at least one of floating gate transistors is a programmed flash cell.

Claim 32

Dependent Claim 285 words

An electronic system, comprising: a processor; and a memory device coupled to the processor, wherein the memory device includes a NOR memory array, the NOR memory array including; a number of vertical pillars formed in rows and columns extending outwardly from a substrate and separated by a number of trenches, wherein each vertical pillar comprises a pair of floating gate transistors on opposing sides of each pillar, including a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, a floating gate separated from the channel region by a first gate insulator in the trenches along rows of pillars, and a control gate separated from the floating gate by a second gate insulator, wherein along columns of the pillars the trench between column adjacent pillars include a pair of floating gates each one opposing the channel regions of the pillar on a respective side of the trench; a number of bit lines coupled to the second source/drain region of each floating gate transistor along rows of the memory array; a number of word lines coupled to the control gate of each floating gate transistor along columns of the memory array; a number of sourcelines formed in a bottom of the trenches between rows of the pillars and coupled to the first source/drain regions of each floating gate transistor along rows of pillars, wherein along rows of the pillars the first source/drain region of each floating gate transistor in column adjacent pillars couples to the sourceline in a shared trench such that each floating gate transistor neighboring the shared trench shares a common sourceline; and wherein at least one of floating gate transistors is a programmed flash cell.

Claim 33

Dependent Claim 29 words

The electronic system of claim 26 , wherein the programmed flash cell includes a charge of approximately 100 electrons trapped on the floating gate of the programmed flash cell.

Claim 34

Dependent Claim 36 words

The electronic system of claim 26 , wherein each floating gate transistor operates as equivalent to a floating gate transistor having a size equal to or less than 2.0 lithographic features squared (2 F 2 ).

Claim 35

Dependent Claim 81 words

The electronic system of claim 26 , wherein, in a read operation, a sourceline for two column adjacent pillars sharing a trench is coupled to a ground potential, the drain regions of the column adjacent pillars sharing a trench are precharged to a fractional voltage of VDD, and the control gate for each of the column adjacent pillars sharing a trench is addressed such that a conductivity state of a floating gate transistor in the NOR memory array can be sensed.

Claim 36

Dependent Claim 69 words

The electronic system of claim 26 , wherein, in a write operation, a sourceline for two column adjacent pillars sharing a trench is biased to a voltage higher than VDD, one of the drain regions of the column adjacent pillars sharing a trench is coupled to a ground potential, and the control gate for each of the column adjacent pillars sharing a trench is addressed with a wordline potential.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2009-02-06	2009-08-08	2010-02-07	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2013-02-06	2013-08-08	2014-02-07	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2017-02-06	2017-08-08	2018-02-07	$7700.00	Window Closed / Lapsed

NOR flash memory cell with high storage density

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