US6611032B2
Expired / Lapsed
US
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Methods for forming wordlines, transistor gates, and conductive interconnects, and wordline, transistor gate, and conductive interconnect structures
Assignee: Micron Technology Inc
•
Filing: 2001-06-11
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Granted: 2003-08-26
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Expires: 2021-06-11
Abstract
Abstract The invention encompasses stacked semiconductor devices including gate stacks, wordlines, PROMs, conductive interconnecting lines, and methods for forming such structures. The invention also includes a method of forming a transistor gate comprising: a) forming gate dielectric layer; b) forming a polysilicon gate layer against the gate dielectric layer; and c) doping the polysilicon gate layer with a conductivity-enhancing dopant, the dopant being provided in a concentration gradient within the polysilicon layer, the concentration gradient increasing in a direction toward the gate dielectric layer. The invention also includes a wordline comprising: a) a polysilicon line; a substantially fluorine impervious barrier layer over the polysilicon line; and a b) layer of metal-silicide over the substantially fluorine impervious barrier layer.
Inventors
- 👤 Klaus Florian Schuegraf
- 👤 Carl Powell
- 👤 Randhir P. S. Thakur
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 16:24
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/60; H10D64/66; H10D64/661; H10D64/662; H10D64/664; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01306; H10D64/01308; H10D64/01312; H10D64/031; H10D64/035
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
52 words
A transistor gate comprising: a gate layer of polysilicon comprising a gradient of dopant concentration that decreases with increasing elevation across an entirety of a thickness of the gate layer; a substantially fluorine impervious barrier layer over the gate layer; and a layer of metal-silicide over the substantially fluorine impervious barrier layer.
Claim 2
Dependent Claim
52 words
A transistor gate comprising: a gate layer of polysilicon comprising a gradient of dopant concentration that decreases with increasing elevation across an entirety of a thickness of the gate layer; a substantially fluorine impervious barrier layer over the gate layer; and a layer of metal-silicide over the substantially fluorine impervious barrier layer.
Claim 3
Dependent Claim
15 words
The transistor gate of claim 1 wherein the substantially fluorine impervious barrier layer comprises TiN.
Claim 4
Dependent Claim
15 words
The transistor gate of claim 1 wherein the substantially fluorine impervious barrier layer comprises nitrogen.
Claim 5
Dependent Claim
55 words
A wordline comprising: a polysilicon line comprising a gradient dopant concentration that decreases with increasing elevation across an entirety of a thickness of the polysilicon line; a substantially fluorine impervious barrier layer over the polysilicon line, the barrier layer comprising an oxygen-comprising material; and a layer of metal-silicide over the substantially fluorine impervious barrier layer.
Claim 6
Dependent Claim
55 words
A wordline comprising: a polysilicon line comprising a gradient dopant concentration that decreases with increasing elevation across an entirety of a thickness of the polysilicon line; a substantially fluorine impervious barrier layer over the polysilicon line, the barrier layer comprising an oxygen-comprising material; and a layer of metal-silicide over the substantially fluorine impervious barrier layer.
Claim 7
Dependent Claim
15 words
The wordline of claim 4 wherein the substantially fluorine impervious barrier layer comprises silicon dioxide.
Claim 8
Dependent Claim
61 words
A transistor gate comprising: a gate dielectric layer over a substrate; a first doped polysilicon layer over the gate dielectric layer; and a second doped polysilicon layer over the first doped polysilicon layer, the second doped polysilicon layer comprising a gradient of dopant concentration that decreases with increasing elevation across an entirety of a thickness of the second doped polysilicon layer.
Claim 9
Dependent Claim
61 words
A transistor gate comprising: a gate dielectric layer over a substrate; a first doped polysilicon layer over the gate dielectric layer; and a second doped polysilicon layer over the first doped polysilicon layer, the second doped polysilicon layer comprising a gradient of dopant concentration that decreases with increasing elevation across an entirety of a thickness of the second doped polysilicon layer.
Claim 10
Dependent Claim
16 words
The transistor gate of claim 6 further comprising a metal-suicide layer over the doped polysilicon layers.
Claim 11
Dependent Claim
16 words
The transistor gate of claim 6 wherein the transistor gate is devoid of a metal-suicide layer.
Claim 12
Dependent Claim
16 words
The transistor gate of claim 6 further comprising a floating gate devoid of a metal-suicide layer.
Claim 13
Dependent Claim
73 words
A wordline comprising: a gate dielectric layer over a substrate; a line of substantially undoped polysilicon over the gate dielectric layer; a line of doped polysilicon over the line of substantially undoped polysilicon, the line of doped polysilicon comprising a gradient of dopant concentration that decreases with increasing elevation across an entirety of a thickness of the line of doped polysilicon; and a substantially fluorine impervious barrier layer over the gate dielectric layer.
Claim 14
Dependent Claim
73 words
A wordline comprising: a gate dielectric layer over a substrate; a line of substantially undoped polysilicon over the gate dielectric layer; a line of doped polysilicon over the line of substantially undoped polysilicon, the line of doped polysilicon comprising a gradient of dopant concentration that decreases with increasing elevation across an entirety of a thickness of the line of doped polysilicon; and a substantially fluorine impervious barrier layer over the gate dielectric layer.
Claim 15
Dependent Claim
13 words
The wordline of claim 10 wherein the barrier layer comprises an oxygen-comprising material.
Claim 16
Dependent Claim
12 words
The wordline of claim 10 wherein the barrier layer comprises silicon dioxide.
Claim 17
Dependent Claim
90 words
A conductive interconnect comprising: a first line of doped polysilicon over a substrate and comprising a gradient of dopant concentration that decreases with increasing elevation across an entirety of a thickness of the first line of doped polysilicon; a second line of doped polysilicon on the first line of doped polysilicon, the first and second lines of doped polysilicon comprising a gradient of dopant concentration across a thickness of the first and second lines of doped polysilicon; and a metal-silicide layer over the first and second lines of doped polysilicon.
Claim 18
Dependent Claim
90 words
A conductive interconnect comprising: a first line of doped polysilicon over a substrate and comprising a gradient of dopant concentration that decreases with increasing elevation across an entirety of a thickness of the first line of doped polysilicon; a second line of doped polysilicon on the first line of doped polysilicon, the first and second lines of doped polysilicon comprising a gradient of dopant concentration across a thickness of the first and second lines of doped polysilicon; and a metal-silicide layer over the first and second lines of doped polysilicon.
Claim 19
Dependent Claim
65 words
A programmable-read-only-memory device comprising: a first dielectric layer over a substrate; a floating gate over the first dielectric layer; a second dielectric layer over the floating gate; a conductive line over the second dielectric layer; a metal-silicide layer over the conductive line; and the conductive line comprising: a first substantially undoped polysilicon layer; and a doped polysilicon layer over the first substantially undoped polysilicon layer.
Claim 20
Dependent Claim
65 words
A programmable-read-only-memory device comprising: a first dielectric layer over a substrate; a floating gate over the first dielectric layer; a second dielectric layer over the floating gate; a conductive line over the second dielectric layer; a metal-silicide layer over the conductive line; and the conductive line comprising: a first substantially undoped polysilicon layer; and a doped polysilicon layer over the first substantially undoped polysilicon layer.
Claim 21
Dependent Claim
12 words
The programmable-read-only-memory device of claim 14 wherein the device is an EPROM.
Claim 22
Dependent Claim
12 words
The programmable-read-only-memory device of claim 14 wherein the device is an EEPROM.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2006-08-25 | 2007-02-24 | 2007-08-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-08-25 | 2011-02-24 | 2011-08-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-08-25 | 2015-02-24 | 2015-08-26 | $7700.00 | Window Closed / Lapsed |