US6040238A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Thermal annealing for preventing polycide void
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 1998-01-08
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Granted: 2000-03-21
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Expires: 2018-01-08
Abstract
Abstract A method for fabricating polycide gate electrodes wherein voids at the silicide/polysilicon interface are eliminated by thermal annealing is described. A layer of gate silicon oxide is grown over the surface of a semiconductor substrate. A polysilicon layer is deposited overlying the gate silicon oxide layer. A silicide layer is formed overlying the polysilicon layer. The semiconductor substrate is annealed by rapid thermal annealing (RTA). Thereafter, an oxide layer is deposited overlying the silicide layer. Because the silicide layer has been annealed, silicon atoms are prevented from diffusing into the silicide layer and forming voids in the polysilicon layer. The silicide, polysilicon and gate silicon oxide layers are patterned to complete fabrication of a gate electrode in the manufacture of an integrated circuit device.
Inventors
- 👤 Chie-Ming Yang
- 👤 Jih-Hwa Wang
- 👤 Yen-Yi Lin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 21:06
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01306; H10D64/01308; H10D64/01312
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
162 words
A method of fabricating gate electrodes in the manufacture of an integrated circuit device comprising: growing a layer of gate silicon oxide over the surface of a semiconductor substrate; depositing a polysilicon layer overlying said gate silicon oxide layer; forming a tungsten silicide layer overlying said polysilicon layer; thermally annealing said tungsten silicide layer at a temperature of 750 to 850° C. for 20 to 60 seconds whereby said tungsten silicide layer is stabilized and stress relaxed; thereafter depositing a hard mask layer overlying said tungsten silicide layer wherein said annealing step prevents silicon atoms from diffusing out of said polysilicon layer into said tungsten silicide layer and causing voids in said polysilicon layer and wherein the absence of said voids prevents the formation of silicon pits in said semiconductor substrate; and patterning said hard mask, said tungsten silicide, said polysilicon and said gate silicon oxide layers to complete fabrication of said gate electrodes in the manufacture of said integrated circuit device.
Claim 2
Independent Claim
162 words
A method of fabricating gate electrodes in the manufacture of an integrated circuit device comprising: growing a layer of gate silicon oxide over the surface of a semiconductor substrate; depositing a polysilicon layer overlying said gate silicon oxide layer; forming a tungsten silicide layer overlying said polysilicon layer; thermally annealing said tungsten silicide layer at a temperature of 750 to 850° C. for 20 to 60 seconds whereby said tungsten silicide layer is stabilized and stress relaxed; thereafter depositing a hard mask layer overlying said tungsten silicide layer wherein said annealing step prevents silicon atoms from diffusing out of said polysilicon layer into said tungsten silicide layer and causing voids in said polysilicon layer and wherein the absence of said voids prevents the formation of silicon pits in said semiconductor substrate; and patterning said hard mask, said tungsten silicide, said polysilicon and said gate silicon oxide layers to complete fabrication of said gate electrodes in the manufacture of said integrated circuit device.
Claim 3
Dependent Claim
28 words
The method according to claim 1 wherein said polysilicon layer is deposited by low pressure chemical vapor deposition to a thickness of between about 500 and 1500 Angstroms.
Claim 4
Dependent Claim
21 words
The method according to claim 1 wherein said tungsten silicide layer has a thickness of between about 1000 and 1500 Angstroms.
Claim 5
Dependent Claim
24 words
The method according to claim 1 wherein said hard mask layer comprises tetraethoxysilane (TEOS) having a thickness of between about 1000 and 2000 Angstroms.
Claim 6
Independent Claim
171 words
A method of fabricating a gate electrode in the manufacture of an integrated circuit device wherein the formation of silicon pits in a semiconductor substrate adjacent to said gate electrode is prevented comprising: growing a layer of gate silicon oxide over the surface of said semiconductor substrate; depositing a polysilicon layer overlying said gate silicon oxide layer; forming a tungsten silicide layer overlying said polysilicon layer; annealing said semiconductor substrate by rapid thermal annealing (RTA) whereby said tungsten silicide layer is stabilized and stress relaxed; thereafter depositing a hard mask layer overlying said tungsten silicide layer wherein said annealing step prevents silicon atoms from diffusing out of said polysilicon layer into said tungsten silicide layer and causing voids in said polysilicon layer and wherein the absence of said voids prevents the formation of said silicon pits in said semiconductor substrate; and patterning said hard mask, said tungsten silicide, said polysilicon and said gate silicon oxide layers to complete fabrication of said gate electrode in the manufacture of said integrated circuit device.
Claim 7
Independent Claim
171 words
A method of fabricating a gate electrode in the manufacture of an integrated circuit device wherein the formation of silicon pits in a semiconductor substrate adjacent to said gate electrode is prevented comprising: growing a layer of gate silicon oxide over the surface of said semiconductor substrate; depositing a polysilicon layer overlying said gate silicon oxide layer; forming a tungsten silicide layer overlying said polysilicon layer; annealing said semiconductor substrate by rapid thermal annealing (RTA) whereby said tungsten silicide layer is stabilized and stress relaxed; thereafter depositing a hard mask layer overlying said tungsten silicide layer wherein said annealing step prevents silicon atoms from diffusing out of said polysilicon layer into said tungsten silicide layer and causing voids in said polysilicon layer and wherein the absence of said voids prevents the formation of said silicon pits in said semiconductor substrate; and patterning said hard mask, said tungsten silicide, said polysilicon and said gate silicon oxide layers to complete fabrication of said gate electrode in the manufacture of said integrated circuit device.
Claim 8
Dependent Claim
28 words
The method according to claim 5 wherein said polysilicon layer is deposited by low pressure chemical vapor deposition to a thickness of between about 500 and 1500 Angstroms.
Claim 9
Dependent Claim
21 words
The method according to claim 5 wherein said tungsten silicide layer has a thickness of between about 1000 to 1500 Angstroms.
Claim 10
Dependent Claim
29 words
The method according to claim 5 wherein said step of annealing said semiconductor substrate is performed at a temperature of 750 to 850° C. for 20 to 60 seconds.
Claim 11
Dependent Claim
24 words
The method according to claim 5 wherein said hard mask layer comprises tetraethoxysilane (TEOS) having a thickness of between about 1000 and 2000 Angstroms.
Claim 12
Independent Claim
169 words
A method of fabricating a gate electrode in the manufacture of an integrated circuit device wherein the formation of silicon pits in a semiconductor substrate adjacent to said gate electrode is prevented comprising: growing a layer of gate silicon oxide over the surface of said semiconductor substrate; depositing a polysilicon layer overlying said gate silicon oxide layer; forming a tungsten silicide layer overlying said polysilicon layer; annealing said semiconductor substrate by rapid thermal annealing (RTA) whereby said tungsten silicide layer is stabilized and stress relaxed; thereafter depositing a TEOS layer overlying said tungsten silicide layer wherein said annealing step prevents silicon atoms from diffusing out of said polysilicon layer into said tungsten silicide layer and causing voids in said polysilicon layer and wherein the absence of said voids prevents the formation of said silicon pits in said semiconductor substrate; and patterning said TEOS, said tungsten silicide, said polysilicon and said gate silicon oxide layers to complete fabrication of said gate electrode in the manufacture of said integrated circuit device.
Claim 13
Independent Claim
169 words
A method of fabricating a gate electrode in the manufacture of an integrated circuit device wherein the formation of silicon pits in a semiconductor substrate adjacent to said gate electrode is prevented comprising: growing a layer of gate silicon oxide over the surface of said semiconductor substrate; depositing a polysilicon layer overlying said gate silicon oxide layer; forming a tungsten silicide layer overlying said polysilicon layer; annealing said semiconductor substrate by rapid thermal annealing (RTA) whereby said tungsten silicide layer is stabilized and stress relaxed; thereafter depositing a TEOS layer overlying said tungsten silicide layer wherein said annealing step prevents silicon atoms from diffusing out of said polysilicon layer into said tungsten silicide layer and causing voids in said polysilicon layer and wherein the absence of said voids prevents the formation of said silicon pits in said semiconductor substrate; and patterning said TEOS, said tungsten silicide, said polysilicon and said gate silicon oxide layers to complete fabrication of said gate electrode in the manufacture of said integrated circuit device.
Claim 14
Dependent Claim
28 words
The method according to claim 10 wherein said polysilicon layer is deposited by low pressure chemical vapor deposition to a thickness of between about 500 and 1500 Angstroms.
Claim 15
Dependent Claim
21 words
The method according to claim 10 wherein said tungsten silicide layer has a thickness of between about 1000 to 1500 Angstroms.
Claim 16
Dependent Claim
29 words
The method according to claim 10 wherein said step of annealing said semiconductor substrate is performed at a temperature of 750 to 850° C. for 20 to 60 seconds.
Claim 17
Dependent Claim
24 words
The method according to claim 10 wherein said hard mask layer comprises tetraethoxysilane (TEOS) having a thickness of between about 1000 and 2000 Angstroms.
Claim 18
Dependent Claim
72 words
The method according to claim 10 further comprising: forming source and drain regions within said semiconductor substrate adjacent to said gate electrode; covering said gate electrode and said source and drain regions with an insulating layer; etching an opening through said insulating layer to one of said underlying source and drain regions; and filling said opening with a conducting layer to complete electrical connections in the fabrication of said integrated circuit device.
References Cited (Backward Citations)
US4833099A
Cited
US5393685A
Cited
US5915197A
Cited
US5434096A
Cited
US5472896A
Cited
US5771110A
Cited
US5777920A
Cited
US5734179A
Cited
US5837568A
Cited
US5904512A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-03-21 | 2003-09-20 | 2004-03-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-03-21 | 2007-09-20 | 2008-03-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-03-21 | 2011-09-20 | 2012-03-21 | $7700.00 | Window Closed / Lapsed |