US5904512A
Expired / Lapsed
US
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Method of making SRAM cell having single layer polysilicon thin film transistors
Assignee: Advanced Micro Devices Inc
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Filing: 1997-07-16
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Granted: 1999-05-18
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Expires: 2017-07-16
Abstract
Abstract A static metal oxide semiconductor random access memory (SRAM) having NMOS and thin film transistors (TFTs) formed from a single polysilicon layer, and a method for forming the same. The SRAM cell comprises a plurality of NMOS transistors and TFTs that are interconnected by a local interconnect structure. The single layer of poly is used to define the TFT bodies and gates of NMOS transistors in the SRAM cell. Each TFT comprises a single polysilicon layer comprising source gate and drain regions. During the fabrication process, exposed portions of the TFT polysilicon body and exposed regions of NMOS transistors react with a refractory metal silicide to form polycide and silicide regions, respectively. An amorphous silicon pattern also reacts with the refractory metal silicide to form a local interconnect structure connecting the silicided portions of the thin film transistors and the MOS transistors. This arrangement results in a TFT SRAM cell that can be implemented using simple fabrication techniques, such as single poly logic processes or ASIC processes.
Inventors
- 👤 Kuang-Yeh Chang
- 👤 Yowjuang W. Liu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 11:33
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/0698; H10B; H10B10/00; H10B10/12; H10B10/125; H10D; H10D86/00; H10D86/01; H10D86/201; Y; Y10; Y10S; Y10S257/00; Y10S257/903
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
174 words
A method for forming an integrated circuit comprising the steps of: (1) forming a polysilicon pattern from polysilicon deposited on a field-oxidized silicon substrate, the polysilicon pattern comprising transistor gates for a first group of transistors and polysilicon bodies for a second group of transistors; (2) implanting portions of the field-oxidized silicon substrate with a first impurity to form source and drain regions for said first group of transistors; (3) implanting said polysilicon bodies with a second impurity to form source and drain regions for said second group of transistors; (4) forming an oxide layer pattern exposing portions of the implanted portions of the field-oxidized silicon substrate and said polysilicon pattern; (5) depositing a refractory metal silicide on the oxide layer pattern; (6) forming an amorphous silicon pattern on the deposited refractory metal silicide; and (7) applying heat to cause said deposited refractory metal silicide to react with said amorphous silicon pattern to form first conducting regions and to react with the portions exposed by said oxide layer pattern to form second conducting regions.
Claim 2
Independent Claim
174 words
A method for forming an integrated circuit comprising the steps of: (1) forming a polysilicon pattern from polysilicon deposited on a field-oxidized silicon substrate, the polysilicon pattern comprising transistor gates for a first group of transistors and polysilicon bodies for a second group of transistors; (2) implanting portions of the field-oxidized silicon substrate with a first impurity to form source and drain regions for said first group of transistors; (3) implanting said polysilicon bodies with a second impurity to form source and drain regions for said second group of transistors; (4) forming an oxide layer pattern exposing portions of the implanted portions of the field-oxidized silicon substrate and said polysilicon pattern; (5) depositing a refractory metal silicide on the oxide layer pattern; (6) forming an amorphous silicon pattern on the deposited refractory metal silicide; and (7) applying heat to cause said deposited refractory metal silicide to react with said amorphous silicon pattern to form first conducting regions and to react with the portions exposed by said oxide layer pattern to form second conducting regions.
Claim 3
Dependent Claim
79 words
A method as recited in claim 1, wherein said step (1) comprises the steps of: field implanting a third impurity through said field-oxidized silicon substrate to isolate said first group of transistors; forming a gate oxide layer in said field-oxidized silicon substrate at regions corresponding to said transistor gates for said first group of transistors; and depositing said polysilicon on said field-oxidized silicon substrate and said gate oxide layer, said transistor gates being formed on corresponding gate oxide layer.
Claim 4
Dependent Claim
56 words
A method as recited in claim 2, wherein said step (1) further comprises the steps of: depositing an insulating oxide layer on said polysilicon pattern; and etching said insulating oxide layer to form insulating spaces at the edges of said polysilicon pattern, said insulating spaces forming a barrier between said polysilicon and said first conducting regions.
Claim 5
Dependent Claim
62 words
A method as recited in claim 1, wherein said step (2) comprises the steps of: depositing a photoresist layer on said polysilicon pattern; etching said photoresist layer to expose portions of said field-oxidized silicon substrate corresponding to said source and drain regions of said first group of transistors; and implanting the exposed portions of said field-oxidized silicon substrate with said first impurity.
Claim 6
Dependent Claim
15 words
A method as recited in claim 4, wherein said first impurity is an N+ impurity.
Claim 7
Dependent Claim
73 words
A method as recited in claim 1, wherein said step (3) comprises the steps of: performing a blanket implant of the field-oxidized silicon substrate and said polysilicon pattern with a third impurity; depositing a photoresist layer; etching said photoresist layer to expose portions of said polysilicon bodies corresponding to said source and drain regions of said second group of transistors; and implanting the exposed portions of said polysilicon bodies with said second impurity.
Claim 8
Dependent Claim
53 words
A method as recited in claim 1, wherein said step (4) comprises the steps of: depositing a resistor protect oxide layer having a thickness of between 300 and 500 angstroms; performing rapid thermal annealing to activate the implanted impurities; and etching the deposited resistor protect oxide layer to form said oxide layer pattern.
Claim 9
Dependent Claim
14 words
A method as recited in claim 1, wherein said refractory metal silicide is titanium.
Claim 10
Dependent Claim
74 words
A method as recited in claim 1, wherein said step (7) comprises the steps of: applying said heat by performing rapid thermal annealing to cause said deposited refractory metal silicide to react with the exposed portions of the implanted portions of the field-oxidized silicon substrate to form silicide and to react with the exposed portions of the polysilicon pattern to form polycide; and stripping unreacted refractory metal silicide from the heated oxide layer pattern.
Claim 11
Dependent Claim
16 words
A method as recited in claim 9, wherein said first conducting region consists essentially of silicide.
Claim 12
Dependent Claim
17 words
A method as recited in claim 1, wherein second conducting regions comprise silicide regions and polycide regions.
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