Method of forming local interconnect structure without P-N junction between active elements

Claim 1

A method of forming an interconnect structure for an integrated circuit device, comprising the steps of: forming an N-channel transistor in a first portion of a substrate, the N-channel transistor having a gate electrode; forming a P-channel transistor in a second portion of the substrate, the P-channel transistor having a gate electrode, wherein both the P-channel transistor and N-channel transistor gate electrodes are doped to have an N-type conductivity; forming an insulating layer over the N-channel and P-channel transistors, including their gate electrodes; forming openings through the insulating layer to expose a portion of the N-channel transistor gate electrode and a portion of a source/drain region of the P-channel transistor; forming a layer of polycrystalline silicon over the insulating layer and in the openings; doping a first portion of the polycrystalline silicon layer, in contact with the N-channel transistor gate electrode, with an N-type dopant; doping a second portion of the polycrystalline silicon layer, in contact with the source/drain region of the P-channel transistor, with a P-type dopant, wherein the first and second portions of the polycrystalline silicon layer are adjacent, wherein a PN junction is formed between them; and forming a refractory metal silicide layer over the polycrystalline silicon to provide a conductive path between the first and second polycrystalline silicon portions which is in parallel with the PN junction.

Claim 2

A method of forming an interconnect structure for an integrated circuit device, comprising the steps of: forming an N-channel transistor in a first portion of a substrate, the N-channel transistor having a gate electrode; forming a P-channel transistor in a second portion of the substrate, the P-channel transistor having a gate electrode, wherein both the P-channel transistor and N-channel transistor gate electrodes are doped to have an N-type conductivity; forming an insulating layer over the N-channel and P-channel transistors, including their gate electrodes; forming openings through the insulating layer to expose a portion of the N-channel transistor gate electrode and a portion of a source/drain region of the P-channel transistor; forming a layer of polycrystalline silicon over the insulating layer and in the openings; doping a first portion of the polycrystalline silicon layer, in contact with the N-channel transistor gate electrode, with an N-type dopant; doping a second portion of the polycrystalline silicon layer, in contact with the source/drain region of the P-channel transistor, with a P-type dopant, wherein the first and second portions of the polycrystalline silicon layer are adjacent, wherein a PN junction is formed between them; and forming a refractory metal silicide layer over the polycrystalline silicon to provide a conductive path between the first and second polycrystalline silicon portions which is in parallel with the PN junction.

Claim 4

The method of claims 1, wherein the step of forming the refractory metal silicide layer comprises the step of depositing a refractory metal silicide over the polycrystalline silicon layer.