High density local interconnect in an integrated circit using metal silicide

Claim 1

A method for interconnecting circuit devices in a body of silicon substrate, said body including CMOS circuit devices, said method comprising the steps of: (a) forming a polysilicon layer on selected areas of said body to contact and interconnect a first set of one or more CMOS devices; (b) forming an electrically insulating layer over selected portions of said polysilicon layer, leaving predetermined portions of a second set of one or more CMOS devices in the substrate body exposed, said second set different from said first set; wherein said exposed portions of the second set include a surface region of a circuit device in the body; (b1) forming an amorphous silicon layer on top of and in contact with said surface region; and (b2) doping said layer to render at least a portion of it electrically conductive, and (c) depositing a metal silicide layer over said insulating layer, said silicide layer having a portion not overlapping the polysilicon layer over said exposed portions of said second set of devices to interconnect said second set of devices; wherein said silicide layer is deposited on said doped amorphous silicon layer portion, so that the silicide layer is electrically connected to said surface region through said doped amorphous silicon layer portion.

Claim 2

A method for interconnecting circuit devices in a body of silicon substrate, said body including CMOS circuit devices, said method comprising the steps of: (a) forming a polysilicon layer on selected areas of said body to contact and interconnect a first set of one or more CMOS devices; (b) forming an electrically insulating layer over selected portions of said polysilicon layer, leaving predetermined portions of a second set of one or more CMOS devices in the substrate body exposed, said second set different from said first set; wherein said exposed portions of the second set include a surface region of a circuit device in the body; (b1) forming an amorphous silicon layer on top of and in contact with said surface region; and (b2) doping said layer to render at least a portion of it electrically conductive, and (c) depositing a metal silicide layer over said insulating layer, said silicide layer having a portion not overlapping the polysilicon layer over said exposed portions of said second set of devices to interconnect said second set of devices; wherein said silicide layer is deposited on said doped amorphous silicon layer portion, so that the silicide layer is electrically connected to said surface region through said doped amorphous silicon layer portion.

Claim 11

A method for forming an interconnect to devices in a body of a silicon semiconductor material, said method comprising the steps of: forming diffusion zones in said body to form a circuit device, said diffusion zones including surface regions at a surface of the body; forming an amorphous silicon layer on top of and in contact with said surface regions; doping said layer to render at least a portion of it electrically conductive; and depositing a metal silicide layer on said doped amorphous silicon layer portion, so that the silicide layer is electrically connected to said surface regions through said doped amorphous silicon layer portion, wherein said doping step includes implanting ions into said amorphous silicon layer and into the body at the surface regions such that the peak of the implant is in the body near the surface of the surface regions.

Claim 12

A method for forming an interconnect to devices in a body of a silicon semiconductor material, said method comprising the steps of: forming diffusion zones in said body to form a circuit device, said diffusion zones including surface regions at a surface of the body; forming an amorphous silicon layer on top of and in contact with said surface regions; doping said layer to render at least a portion of it electrically conductive; and depositing a metal silicide layer on said doped amorphous silicon layer portion, so that the silicide layer is electrically connected to said surface regions through said doped amorphous silicon layer portion, wherein said doping step includes implanting ions into said amorphous silicon layer and into the body at the surface regions such that the peak of the implant is in the body near the surface of the surface regions.

Claim 14

A method for forming an interconnect to devices in a body of a silicon semiconductor material, said body including a circuit device having a surface region, said method comprising the steps of: forming an amorphous silicon layer on top of and in contact with said surface region; doping said layer to render at least a portion of it electrically conductive; and forming a metal silicide layer on said doped amorphous silicon layer portion, so that the silicide layer is electrically connected to said surface region through said doped amorphous silicon layer portion, said circuit device including a N+ and a P+ surface region, said forming step including forming the amorphous layer on top of and in contact with said N+ and P+ regions, wherein said doping step is such that a portion of the amorphous silicon layer in contact with said N+ region is doped N+ and a portion of the amorphous silicon layer in contact with said P+ region is doped P+, said doping step leaving undoped at least a portion of the amorphous silicon layer separating the N+ and P+ doped amorphous silicon layer portions, thereby preventing the formation of undesirable PN junctions.

Claim 15

A method for forming an interconnect to devices in a body of a silicon semiconductor material, said body including a circuit device having a surface region, said method comprising the steps of: forming an amorphous silicon layer on top of and in contact with said surface region; doping said layer to render at least a portion of it electrically conductive; and forming a metal silicide layer on said doped amorphous silicon layer portion, so that the silicide layer is electrically connected to said surface region through said doped amorphous silicon layer portion, said circuit device including a N+ and a P+ surface region, said forming step including forming the amorphous layer on top of and in contact with said N+ and P+ regions, wherein said doping step is such that a portion of the amorphous silicon layer in contact with said N+ region is doped N+ and a portion of the amorphous silicon layer in contact with said P+ region is doped P+, said doping step leaving undoped at least a portion of the amorphous silicon layer separating the N+ and P+ doped amorphous silicon layer portions, thereby preventing the formation of undesirable PN junctions.