Method for making silicide interconnection structures for integrated circuit devices

Claim 3

A method of forming a conducting path as recited in claim 1 wherein the amorphous silicon is fully consumed in the reaction with the refractory metal.

Claim 4

A method of forming a conducting path as recited in claim 1 and further comprising the steps of: forming a passivation layer over said integrated circuit and said silicide strip; forming a hole through said passivation layer to a location on said silicide strip in the contact region; and forming a contact with the silicide strip through the hole.

Claim 5

A method of forming a conducting path as recited in claim 1 wherein said layer of refractory metal and said layer of amorphous silicon are formed by sputter deposition.

Claim 6

A method of forming a conducting path as recited in claim 1 wherein the step of patterning further comprises etching said amorphous silicon to form a pattern, and wherein said refractory metal layer serves as an etch stop.

Claim 7

In an integrated circuit including a plurality of devices separated by sections of field oxide, a method of forming an electrical connection with a junction region of one of said devices, the method comprising the steps of: forming a layer of refractory metal over at least a junction region of a device and at least a portion of an adjacent section of field oxide; forming a layer of amorphous silicon over said layer of refractory metal; patterning said amorphous silicon to form a strip, the strip extending over and between the field oxide and the junction region but stopping short of a gate region adjacent the junction region; heating said integrated circuit to cause that portion of the metal which is covered by the strip of amorphous silicon to react therewith and to cause that portion of the metal which overlies the junction region adjacent the gate region to react with a surface part of the junction region to form a strip of electrically conducting silicide which is in electrical contact with the junction region adjacent the gate region and which extends from the junction region over the field oxide; and removing the portions of said refractory metal layer which did not react with said strip of amorphous silicon to form said silicide strip.

Claim 8

In an integrated circuit including a plurality of devices separated by sections of field oxide, a method of forming an electrical connection with a junction region of one of said devices, the method comprising the steps of: forming a layer of refractory metal over at least a junction region of a device and at least a portion of an adjacent section of field oxide; forming a layer of amorphous silicon over said layer of refractory metal; patterning said amorphous silicon to form a strip, the strip extending over and between the field oxide and the junction region but stopping short of a gate region adjacent the junction region; heating said integrated circuit to cause that portion of the metal which is covered by the strip of amorphous silicon to react therewith and to cause that portion of the metal which overlies the junction region adjacent the gate region to react with a surface part of the junction region to form a strip of electrically conducting silicide which is in electrical contact with the junction region adjacent the gate region and which extends from the junction region over the field oxide; and removing the portions of said refractory metal layer which did not react with said strip of amorphous silicon to form said silicide strip.

Claim 9

The method recited in claim 6 wherein said step of patterning said layer of amorphous silicon includes etching said amorphous silicon, wherein said layer of refractory metal serves as an etch stop.

Claim 10

A method as recited in claim 6 and further comprising the steps of: forming a passivation layer over said device and said adjacent section of field oxide; forming a contact hole through said passivation layer to a portion of said silicide strip which overlies said section of field oxide; and forming a contact with the silicide strip through the hole.

Claim 11

In an integrated circuit including a pair of devices and an intervening section of field oxide, a method of interconnecting a junction region of one of the devices with a part of the other device, the method comprising the steps of: forming a layer of refractory metal over at least a portion of an integrated circuit which includes a junction region of a first device, a second deice having a part which is to be interconnected with said junction region, and a section of intervening field oxide; forming a layer of amorphous silicon over said layer of refractory metal; patterning said amorphous silicon into an elongated strip the strip extending between said part and said junction region but stopping short of a gate region adjacent said junction region; heating said integrated circuit to cause that portion of the metal which is covered by the strip of amorphous silicon to react therewith and to cause that portion of the metal which overlies the junction region adjacent the gate region to react with a surface part of the junction region to form a strip of electrically conducting silicide which is in electrical contact with the junction region adjacent the gate region and which extends between the junction region and said part of the second device; and removing the portions of said refractory metal layer which did not react with said strip of amorphous silicon to form said silicide strip.

Claim 12

In an integrated circuit including a pair of devices and an intervening section of field oxide, a method of interconnecting a junction region of one of the devices with a part of the other device, the method comprising the steps of: forming a layer of refractory metal over at least a portion of an integrated circuit which includes a junction region of a first device, a second deice having a part which is to be interconnected with said junction region, and a section of intervening field oxide; forming a layer of amorphous silicon over said layer of refractory metal; patterning said amorphous silicon into an elongated strip the strip extending between said part and said junction region but stopping short of a gate region adjacent said junction region; heating said integrated circuit to cause that portion of the metal which is covered by the strip of amorphous silicon to react therewith and to cause that portion of the metal which overlies the junction region adjacent the gate region to react with a surface part of the junction region to form a strip of electrically conducting silicide which is in electrical contact with the junction region adjacent the gate region and which extends between the junction region and said part of the second device; and removing the portions of said refractory metal layer which did not react with said strip of amorphous silicon to form said silicide strip.

Claim 13

The method recited in claim 9 wherein said step of patterning said layer of amorphous silicon includes etching said amorphous silicon, wherein said layer of refractory metal serves as an etch stop.

Claim 14

A method of forming a connection as recited in claim 9 and further comprising forming a passivation layer over said first device, said second device, and said section of field oxide.

Claim 15

A method of forming a connection as recited in claim 6 wherein the amorphous silicon is fully consumed in the reaction with the refractory metal.

Claim 16

A method of forming a connection as recited in claim 10 wherein the amorphous silicon is fully consumed in the reaction with the refractory metal.

Claim 17

A method of forming a connection as recited in claim 11 and further comprising the steps of forming a contact hole through the passivation layer to a portion of the silicide path which overlies said section of field oxide and forming a contact with the silicide strip through the hole.