Interconnection of opposite conductivity type semiconductor regions

Claim 2

A semiconductor memory circuit, comprising: a body of silicon single crystal semiconductor material having at least two cross-coupled bipolar transistors formed in a memory cell therein, wherein each of said transistors includes electrical base, collector, and emitter regions, said transistors being arranged in an improved dense layout, said layout including a sufficiently low voltage drop electrical interconnection forming said cross-coupling between an electrical base region of one transistor and an electrical collector region of the second transistor, said cross-coupling interconnection comprising: a refractory metal silicide layer contacting one of said base or collector regions in one of said first and second transistors and forming an electrical contact therewith, and a polycrystalline silicon layer in contact with the other of said base or collector regions in the other of said first and second-transistors and sufficiently doped to form a sufficiently low voltage drop electrical contact therewith, said polycrystalline layer also being in contact with said layer of refractory metal silicide and forming a multi-level sandwich structure, an electrical insulation layer formed over said silicide layer and said polycrystalline silicon layer, a first electrical conductor located on said insulation layer and extending over the area in which said electrical interconnection is formed, at least one additional electrical conductor formed in the same fabrication level as said first conductor and located laterally outside of the area occupied by said interconnection, additional bipolar transistors electrically connected to said first conductor and said additional conductor, and to said two bipolar transistors, said additional bipolar transistors being located in said semiconductor material and between said two bipolar transistors.

Claim 3

A semiconductor memory circuit comprising a body of single crystal semiconductor material having two cross-coupled bipolar transistors formed in a memory cell therein wherein each said bipolar transistor includes electrical base, collector, and emitter regions, an electrical interconnection coupling said two transistors and forming said cross coupling between an electrical base region of one transistor and an electrical collector region of the second transistor, said cross-coupling electrical interconnection being comprised of: a first polysilicon layer of a first conductivity-type being in contact with said base region of one transistor, the doping level of said first polysilicon layer being sufficiently high that a sufficiently low voltage drop electrical contact is formed to said base region, a refractory metal silicide layer in contact with said first polysilicon layer, and a second polysilicon layer of opposite conductivity-type in contact with said collector region of said second transistor and having a sufficiently high doping level to provide a sufficiently low voltage drop contact to said collector region, said second polysilicon layer also being in contact with said refractory metal silicide layer, where said silicide layer is located between said first and second polysilicon layers in a multilayer sandwich structure, a layer of oxide insulation on said polysilicon layers, a first electrical conductor located over said oxide insulation and extending over the area in which said first and second polysilicon layers form said electrical interconnection to said base and collector regions, at least one additional electrical conductor formed in the same fabrication level as said first conductor and located laterally outside the area occupied by said first conductor, an additional bipolar transistor electrically connected to at least one of said first conductor and said additional conductor, and to at least one of said two bipolar transistors, said additional bipolar transistor being located in said semiconductor material and between said two bipolar transistors.

Claim 4

A semiconductor memory circuit comprising a body of single crystal semiconductor material having two cross-coupled bipolar transistors formed in a memory cell therein wherein each said bipolar transistor includes electrical base, collector, and emitter regions, an electrical interconnection coupling said two transistors and forming said cross coupling between an electrical base region of one transistor and an electrical collector region of the second transistor, said cross-coupling electrical interconnection being comprised of: a first polysilicon layer of a first conductivity-type being in contact with said base region of one transistor, the doping level of said first polysilicon layer being sufficiently high that a sufficiently low voltage drop electrical contact is formed to said base region, a refractory metal silicide layer in contact with said first polysilicon layer, and a second polysilicon layer of opposite conductivity-type in contact with said collector region of said second transistor and having a sufficiently high doping level to provide a sufficiently low voltage drop contact to said collector region, said second polysilicon layer also being in contact with said refractory metal silicide layer, where said silicide layer is located between said first and second polysilicon layers in a multilayer sandwich structure, a layer of oxide insulation on said polysilicon layers, a first electrical conductor located over said oxide insulation and extending over the area in which said first and second polysilicon layers form said electrical interconnection to said base and collector regions, at least one additional electrical conductor formed in the same fabrication level as said first conductor and located laterally outside the area occupied by said first conductor, an additional bipolar transistor electrically connected to at least one of said first conductor and said additional conductor, and to at least one of said two bipolar transistors, said additional bipolar transistor being located in said semiconductor material and between said two bipolar transistors.