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US4160989A Expired / Lapsed US ⏱️ 0.0 years remaining

Integrated circuit having complementary bipolar transistors

Assignee: US Philips Corp
•
Filing: 1978-03-17
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Granted: 1979-07-10
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Expires: 1998-03-17
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Abstract

Abstract An integrated circuit having one vertical and one lateral bipolar transistor, including a semiconductor substrate, a deposited semiconductor layer, and connection tracks consisting of portions of the semiconductor layer over a dielectric, other portions of the semiconductor layer being used to form contacts for certain active zones of the transistors.

Inventors

  • 👤 Michel DE Brebisson
  • 👤 Jean-Michel Decrouen
  • 👤 Wolfgang F. J. Edlinger
  • 👤 Jean-Pierre H. Biet

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-24 02:21
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/60; H10D84/65; H10W; H10W20/00; H10W20/01; H10W72/00; Y; Y10; Y10S; Y10S148/00; Y10S148/124

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 154 words
An integrated circuit comprising: a semiconductor substrate portion of a first conductivity type; a plurality of regions of semiconductor material of a second conductivity type on said substrate portion; regions of first insulating material adjoining said semiconductor regions, and extending at least partially thereover; a semiconducting layer of first type conductivity extending partially over said regions of insulating material forming a connection track and partially over said semiconductor regions, said semiconducting layer comprising a monocrystalline portion and a polycrystalline portion; a first bipolar npn transistor having first, second and third vertically arranged successive zones, said first zone being located in said substrate region, said second zone forming the base of the first transistor and located in one of said second type semiconductor regions, and said third zone located in said monocrystalline portion of said semiconductor layer and located on said one semiconductor region, said second zone separating said third zone from said substrate region.
Claim 2
Dependent Claim 154 words
An integrated circuit comprising: a semiconductor substrate portion of a first conductivity type; a plurality of regions of semiconductor material of a second conductivity type on said substrate portion; regions of first insulating material adjoining said semiconductor regions, and extending at least partially thereover; a semiconducting layer of first type conductivity extending partially over said regions of insulating material forming a connection track and partially over said semiconductor regions, said semiconducting layer comprising a monocrystalline portion and a polycrystalline portion; a first bipolar npn transistor having first, second and third vertically arranged successive zones, said first zone being located in said substrate region, said second zone forming the base of the first transistor and located in one of said second type semiconductor regions, and said third zone located in said monocrystalline portion of said semiconductor layer and located on said one semiconductor region, said second zone separating said third zone from said substrate region.
Claim 3
Dependent Claim 68 words
An integrated circuit as defined in claim 1, further comprising: a second bipolar pnp transistor comprising two adjacent ones of said regions of semiconductor material with an n-type region therebetween having an impurity doping concentration less than that of said substrate portion; and a band of second insulating material at least partially bounding said p-type regions of semiconductor material and extending in depth down to said substrate portion.
Claim 4
Dependent Claim 54 words
An integrated circuit as claimed in claim 1, further comprising a network of conductor tracks separated from said semiconductor layer by an insulating layer, a polycrystalline portion of said semiconductor layer being supported entirely by one of said regions of insulating material and being connected in two places to said network of conductor tracks.
Claim 5
Dependent Claim 29 words
An integrated circuit as defined in claim 1, wherein said region of second conductivity type on said substrate directly adjoins said semiconductor substrate portion of a first conductivity type.
Claim 6
Dependent Claim 275 words
An integrated circuit comprising: a semiconductor body having a substrate portion of a first conductivity type; a plurality of semiconductor regions of the second conductivity type opposite to the first on said substrate portion, each of said regions having substantially the same thickness; first regions of insulating material adjoining said semiconductor regions, and extending at least partially thereover; a first bipolar vertical npn transistor having first, second, and third zones, said first zone located in the substrate portion, said second zone forming the base of said transistor and located in one of said semiconductor regions, and said third zone of the first conductivity type located on said one semiconductor region separating said third zone from the substrate portion, second regions of insulating material comprising a band of insulating material bounding at least partially said semiconductor regions of the second conductivity type, a second bipolar pnp transistor comprising two adjacent ones of said regions of semiconductor material with an n-type region therebetween having an impurity doping concentration less than that of said substrate portion; a semiconductor layer of the first conductivity type extending partially over said insulating regions and forming a connection track, and extending partially over said ones semiconductor region, said base zone of the first transistor being located for forming a contact with said third zone, said band of insulating material extending in depth down to said substrate portion; and a network of conductor tracks separated from said semiconductor layer by an insulating layer, a polycrystalline portion of said semiconductor layer being supported entirely by one of said regions of insulating material and being connected in two places to said network of conductor tracks.
Claim 7
Dependent Claim 275 words
An integrated circuit comprising: a semiconductor body having a substrate portion of a first conductivity type; a plurality of semiconductor regions of the second conductivity type opposite to the first on said substrate portion, each of said regions having substantially the same thickness; first regions of insulating material adjoining said semiconductor regions, and extending at least partially thereover; a first bipolar vertical npn transistor having first, second, and third zones, said first zone located in the substrate portion, said second zone forming the base of said transistor and located in one of said semiconductor regions, and said third zone of the first conductivity type located on said one semiconductor region separating said third zone from the substrate portion, second regions of insulating material comprising a band of insulating material bounding at least partially said semiconductor regions of the second conductivity type, a second bipolar pnp transistor comprising two adjacent ones of said regions of semiconductor material with an n-type region therebetween having an impurity doping concentration less than that of said substrate portion; a semiconductor layer of the first conductivity type extending partially over said insulating regions and forming a connection track, and extending partially over said ones semiconductor region, said base zone of the first transistor being located for forming a contact with said third zone, said band of insulating material extending in depth down to said substrate portion; and a network of conductor tracks separated from said semiconductor layer by an insulating layer, a polycrystalline portion of said semiconductor layer being supported entirely by one of said regions of insulating material and being connected in two places to said network of conductor tracks.

References Cited (Backward Citations)

US3977019A Cited
US3978515A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1982-07-09 1983-01-08 1983-07-10 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1986-07-09 1987-01-08 1987-07-10 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1990-07-09 1991-01-08 1991-07-10 $7700.00 Window Closed / Lapsed

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