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JPS5688366A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor device

Assignee: Fujitsu Ltd
•
Filing: 1979-12-21
•
Granted: —
•
Expires: 1999-12-21
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Abstract

Abstract PURPOSE:To obtain an MIS transistor having no signal delay by forming the gate electrode thereof in two-layer architecture of metallic silicide underlain with a polycrystalline Si layer and forming a wire on a gate dielectric film of a single metallic silicide layer. CONSTITUTION:A thick field SiO2 film 4 is formed on the periphery of a p type Si substrate 2, and n<+> type source and drain regions 6 and 8 are diffused in the substrate 2 surrounded thereby. Then, a gate SiO2 film 10 is formed on the surface of the substrate 2 exposed between the regions 6 and 8, and when a gate electrode is mounted thereon, a laminate of a polycrystalline Si layer 12 and an Mo silicide layer 14 are formed as a gate electrode with the layer 12 underlaid. When a wiring layer (not shown) is formed on the insulating film, single Mo silicide layer is used. Thus, it can overcome the demerits without losing the advantages of both the polycrystalline Si and the Mo silicide and can accelerate the operation of the device.

Inventors

  • 👤 Masao Taguchi
  • 👤 Nobuo Toyokura

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-06 11:44
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/60; H10D64/66; H10D64/661; H10D64/662

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