US4559694A
Expired / Lapsed
US
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Method of manufacturing a reference voltage generator device
Assignee: Hitachi Ltd
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Filing: 1983-04-12
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Granted: 1985-12-24
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Expires: 2003-04-12
Abstract
Abstract A method is provided for manufacturing a reference voltage generator device which detects a voltage corresponding to an energy gap of a semiconductor, or a voltage of a value close thereto, or a voltage based on an energy level of a semiconductor, and generates the detected voltage as a reference voltage. The reference voltage is generated by detecting a difference of threshold voltages of first and second insulated gate field-effect transistors (IGFETs). Gate electrodes of the first and second IGFETs are formed on gate insulating films which are formed on different surface areas of an identical semiconductor substrate under substantially the same conditions. The gate electrodes of the first and second IGFETs are respectively made of two semiconductors which are selected from among a semiconductor of a first conductivity type, a semiconductor of a second conductivity type and an intrinsic semiconductor made of an identical semiconductor material, but which have Fermi energy levels of values different from each other.
Inventors
- 👤 Kanji Yoh
- 👤 Osamu Yamashiro
- 👤 Satoshi Meguro
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 07:37
CPC Classifications
G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/24; G05F3/242; G05F3/245; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/411; G11C11/4113; G11C11/413; G11C11/417; G11C5/00; G11C5/14; G11C5/143; G11C5/147; H; H03; H03F; H03F3/00; H03F3/45; H03F3/45071; H03F3/45076; H03F3/45179; H03F3/45479; H03F3/45632; H03F3/45744; H03K; H03K19/00; H03K19/003; H03K19/00369; H03K19/00384; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/018514; H03K3/00; H03K3/02; H03K3/023; H03K3/0231; H03K3/0233; H03K3/02337; H03K3/353; H03K3/356; H03K3/3565; H03K5/00; H03K5/22; H03K5/24; H03K5/2472; H03K5/2481; H10; H10D; H10D64/00; H10D64/60; H10D64/66; H10D64/671; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H03F2203/00; H03F2203/45; H03F2203/45394; H10D84/8311; H10D84/83125; H10D84/83138; Y; Y10; Y10S; Y10S148/00; Y10S148/053; Y10S148/07
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
297 words
A method of manufacturing a semiconductor device with at least a pair of insulated gate field-effect transistors having semiconductor gate electrodes of different conductivity type, comprising the steps of: forming an insulating film over a major surface of a semiconductor substrate at a first portion thereof and at a second portion thereof, said first and second portions being of a first conductivity type and being formed in a same part of the semiconductor substrate extending to the major surface thereof, and forming a semiconductor layer over said insulating film overlying said first and second portions; introducing an impurity of the first conductivity type into a first portion of said semiconductor layer overlain at said first portion except for into another portion of said semiconductor layer overlain at said second portion, to provide an impurity level of said impurity of the first conductivity type at that portion; removing said semiconductor layer to form first and second semiconductor gate electrodes at said first and second portions respectively; and selectively introducing an impurity of a second conductivity type opposite to the first conductivity type into said first and second portions not covered with said first and second semiconductor gate electrodes and into said first and second semiconductor gate electrodes so as to provide at those portions an impurity level of the second conductivity type lower than said impurity level of the impurity of the first conductivity type at said first semiconductor gate electrode, thereby to form source and drain semiconductor regions of the second conductivity type on opposite sides of each of said first and second gate electrodes and thereby to define the second semiconductor gate electrode as of the second conductivity type without converting said first semiconductor gate electrode from the first conductivity type to the second conductivity type.
Claim 2
Independent Claim
297 words
A method of manufacturing a semiconductor device with at least a pair of insulated gate field-effect transistors having semiconductor gate electrodes of different conductivity type, comprising the steps of: forming an insulating film over a major surface of a semiconductor substrate at a first portion thereof and at a second portion thereof, said first and second portions being of a first conductivity type and being formed in a same part of the semiconductor substrate extending to the major surface thereof, and forming a semiconductor layer over said insulating film overlying said first and second portions; introducing an impurity of the first conductivity type into a first portion of said semiconductor layer overlain at said first portion except for into another portion of said semiconductor layer overlain at said second portion, to provide an impurity level of said impurity of the first conductivity type at that portion; removing said semiconductor layer to form first and second semiconductor gate electrodes at said first and second portions respectively; and selectively introducing an impurity of a second conductivity type opposite to the first conductivity type into said first and second portions not covered with said first and second semiconductor gate electrodes and into said first and second semiconductor gate electrodes so as to provide at those portions an impurity level of the second conductivity type lower than said impurity level of the impurity of the first conductivity type at said first semiconductor gate electrode, thereby to form source and drain semiconductor regions of the second conductivity type on opposite sides of each of said first and second gate electrodes and thereby to define the second semiconductor gate electrode as of the second conductivity type without converting said first semiconductor gate electrode from the first conductivity type to the second conductivity type.
Claim 3
Dependent Claim
46 words
A method according to claim 1, wherein before the step of introducing the impurity of said second conductivity type, an insulating film is formed on said first semiconductor gate electrode to serve as a mask to the introduction of the impurity of said second conductivity type.
Claim 4
Dependent Claim
22 words
A method according to claim 1, wherein said first conductivity type is the N-type, and said second conductivity type is the P-type.
Claim 5
Dependent Claim
15 words
A method according to claim 3, wherein said semiconductor layer is made of polycrystalline silicon.
Claim 6
Dependent Claim
35 words
A method according to claim 1, wherein said same part of the semiconductor substrate constitutes a well of the first conductivity type, with a remainder of the semiconductor substrate being of said second conductivity type.
Claim 7
Dependent Claim
29 words
A method according to claim 1, wherein said same part of the semiconductor substrate, as well as a remainder of the semiconductor substrate, are of said first conductivity type.
Claim 8
Dependent Claim
34 words
A method according to claim 1, including the step of preparing said semiconductor substrate having said first and second portions of said first conductivity type prior to the step of forming the insulating film.
Claim 9
Dependent Claim
63 words
A method according to claim 7, wherein the step of preparing said semiconductor substrate includes forming a well region of the first conductivity type in a semiconductor body of the second conductivity type, to thereby form a semiconductor substrate having said first and second portions constituted by said well region, with a remainder of the semiconductor substrate being of the second conductivity type.
Claim 10
Dependent Claim
32 words
A method according to claim 1, wherein the level of the density of the impurity doping of the first conductivity type is at least 1.5 times that of the second conductivity type.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-12-23 | 1989-06-24 | 1989-12-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-12-23 | 1993-06-24 | 1993-12-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-12-23 | 1997-06-24 | 1997-12-24 | $7700.00 | Window Closed / Lapsed |