US5336916A
Expired / Lapsed
US
⏱️ 0.0 years remaining
SRAM cell and structure with polycrystalline p-channel load devices
Assignee: STMicroelectronics lnc USA
•
Filing: 1992-07-27
•
Granted: 1994-08-09
•
Expires: 2012-07-27
Abstract
Abstract An integrated circuit structure is suitable for use with SRAM memory devices. P-channel load devices are used in a 6-transistor SRAM cell. The P-channel devices are formed as polycrystalline silicon field effect transistors above the N-channel field effect transistors, which are formed in the substrate. In order to avoid formation of a P-N junction, a barrier layer is formed between P-type and N-type source/drain regions. The preferred barrier is a bilayer formed from a conductive material such as silicide over a doped polycrystalline silicon layer.
Inventors
- 👤 Tsiu C. Chan
- 👤 Frank R. Bryant
- 👤 Lisa K. Jorgenson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 18:20
CPC Classifications
H; H10; H10B; H10B10/00; H10B10/12; H10B10/125; Y; Y10; Y10S; Y10S257/00; Y10S257/903
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
226 words
A structure consisting of a portion of a semiconductor integrated circuit, comprising: a substrate; a first field effect transistor formed within the substrate, and having a gate electrode separated therefrom by a gate oxide layer; a second field effect transistor formed within the substrate, and having a gate electrode separated therefrom by a gate oxide layer, the second transistor gate electrode further extending over a portion of a field oxide layer formed within the substrate; a first insulating layer disposed over a portion of the substrate and the first and second transistor gate electrodes, with an opening to expose a source/drain region of the first transistor and a portion of the second transistor gate electrode; a doped polysilicon layer over a portion of the first insulating layer and in the opening; a conductive barrier layer overlying the doped polysilicon layer, wherein the doped polysilicon layer and the barrier layer define an intermediate interconnect layer in a shared contact opening; a second insulating layer disposed over the intermediate interconnect layer and the first insulating layer, the second insulating layer having an opening therein to expose a portion of the intermediate interconnect layer; a polysilicon interconnect layer over the second insulating layer and contacting the intermediate interconnect layer through the opening in the second insulating layer, wherein a field effect transistor is formed in the polysilicon interconnect layer.
Claim 2
Dependent Claim
226 words
A structure consisting of a portion of a semiconductor integrated circuit, comprising: a substrate; a first field effect transistor formed within the substrate, and having a gate electrode separated therefrom by a gate oxide layer; a second field effect transistor formed within the substrate, and having a gate electrode separated therefrom by a gate oxide layer, the second transistor gate electrode further extending over a portion of a field oxide layer formed within the substrate; a first insulating layer disposed over a portion of the substrate and the first and second transistor gate electrodes, with an opening to expose a source/drain region of the first transistor and a portion of the second transistor gate electrode; a doped polysilicon layer over a portion of the first insulating layer and in the opening; a conductive barrier layer overlying the doped polysilicon layer, wherein the doped polysilicon layer and the barrier layer define an intermediate interconnect layer in a shared contact opening; a second insulating layer disposed over the intermediate interconnect layer and the first insulating layer, the second insulating layer having an opening therein to expose a portion of the intermediate interconnect layer; a polysilicon interconnect layer over the second insulating layer and contacting the intermediate interconnect layer through the opening in the second insulating layer, wherein a field effect transistor is formed in the polysilicon interconnect layer.
Claim 3
Dependent Claim
17 words
The structure of claim 1, wherein the barrier layer of the intermediate interconnect layer is a silicide.
Claim 4
Dependent Claim
17 words
The structure of claim 1, wherein the doped polysilicon layer of the intermediate interconnect layer is N-type.
Claim 5
Dependent Claim
17 words
The structure of claim 3, wherein the barrier layer of the intermediate interconnect layer is a silicide.
Claim 6
Dependent Claim
93 words
The structure of claim 1, wherein the field effect transistor formed in the polysilicon interconnect structure comprises: a gate polysilicon interconnect layer, wherein a portion thereof contacts the conductive barrier layer through the opening in the second insulating layer; a gate insulating layer in contact with a portion of the gate polysilicon interconnect layer; and an upper polysilicon interconnect layer overlying the gate insulating layer, wherein the upper polysilicon interconnect layer contains doped regions defining source/drain regions and a channel region separated from the gate polysilicon interconnect layer by the gate insulating layer.
References Cited (Backward Citations)
US5028975A
Cited
US4569122A
Cited
US4581623A
Cited
US4814841A
Cited
US5132771A
Cited
US5151387A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-08-08 | 1998-02-07 | 1998-08-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-08-08 | 2002-02-07 | 2002-08-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-08-08 | 2006-02-07 | 2006-08-09 | $7700.00 | Window Closed / Lapsed |