US4581623A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Interlayer contact for use in a static RAM cell
Assignee: NXP USA Inc
•
Filing: 1984-05-24
•
Granted: 1986-04-08
•
Expires: 2004-05-24
Abstract
Abstract A CMOS static RAM, which has P channel transistors formed in a second polysilicon layer, N channel transistors formed in the substrate, and gates of both the N channel and P channel transistors formed in a first polysilicon layers, requires that ohmic contact be made between semiconductor material of differing conductivity type. The first polysilicon layer is N-type, and the second polysilicon layer is P-type. Ohmic contact therebetween is achieved by providing a silicide layer which is between these two layers and in physical contact with both. Ohmic contact between N-type regions in the substrate and the second polysilicon layer is similarly achieved by sandwiching silicide therebetween.
Inventors
- 👤 Karl L. Wang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 20:19
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10D64/0114; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/064; H10W20/066; Y; Y10; Y10S; Y10S148/00; Y10S148/019; Y10S148/147; Y10S148/164; Y10S257/00; Y10S257/903
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
364 words
A CMOS static RAM cell formed in a semiconductor substrate, comprising: a first N channel transistor having a drain formed in a first region of a first conductivity type in the substrate, a source formed in a second region of the substrate and coupled to a first power supply terminal, and a gate formed in a first portion of a first polysilicon layer of the first conductivity type; a first P channel transistor having a drain formed in a first portion of a second polysilicon layer of a second conductivity type and in ohmic contact with the drain of the first N channel transistor, a source formed in a second portion of the second polysilicon layer and coupled to a second power supply terminal, and a gate formed in the first portion of the first polysilicon layer in common with the gate of the first N channel transistor; a second N channel transistor having a drain formed in a third region of the first conductivity type in the substrate and coupled to the gate of the first N channel transistor and the first P channel transistor, a source formed in the second region of the substrate and coupled to the first power supply terminal, and a gate formed in a second portion of the first polysilicon layer of the first conductivity type and in ohmic contact with the drain of the first P channel transistor; and a second P channel transistor having a source formed in a third portion of the second polysilicon layer and coupled to the second power supply terminal, a drain formed in a fourth portion of the second polysilicon layer and coupled to the drain of the second N channel transistor, and a gate formed in common with the gate of the second N channel transistor; wherein the ohmic contact between the gates of the second N and P channel transistors and the drain of the first P channel transistor is obtained by having a first portion of a silicide layer sandwiched between at least a portion of the first portion of the second polysilicon layer and at least a portion of the second portion of the first polysilicon layer.
Claim 2
Dependent Claim
364 words
A CMOS static RAM cell formed in a semiconductor substrate, comprising: a first N channel transistor having a drain formed in a first region of a first conductivity type in the substrate, a source formed in a second region of the substrate and coupled to a first power supply terminal, and a gate formed in a first portion of a first polysilicon layer of the first conductivity type; a first P channel transistor having a drain formed in a first portion of a second polysilicon layer of a second conductivity type and in ohmic contact with the drain of the first N channel transistor, a source formed in a second portion of the second polysilicon layer and coupled to a second power supply terminal, and a gate formed in the first portion of the first polysilicon layer in common with the gate of the first N channel transistor; a second N channel transistor having a drain formed in a third region of the first conductivity type in the substrate and coupled to the gate of the first N channel transistor and the first P channel transistor, a source formed in the second region of the substrate and coupled to the first power supply terminal, and a gate formed in a second portion of the first polysilicon layer of the first conductivity type and in ohmic contact with the drain of the first P channel transistor; and a second P channel transistor having a source formed in a third portion of the second polysilicon layer and coupled to the second power supply terminal, a drain formed in a fourth portion of the second polysilicon layer and coupled to the drain of the second N channel transistor, and a gate formed in common with the gate of the second N channel transistor; wherein the ohmic contact between the gates of the second N and P channel transistors and the drain of the first P channel transistor is obtained by having a first portion of a silicide layer sandwiched between at least a portion of the first portion of the second polysilicon layer and at least a portion of the second portion of the first polysilicon layer.
Claim 3
Dependent Claim
66 words
The CMOS static RAM cell of claim 1 wherein the ohmic contact between the first region of the substrate and the first portion of the second polysilicon layer is formed by having a second portion of the silicide layer sandwiched between at least a portion of the first portion of the second polysilicon layer and at least a portion of the first region of the substrate.
Claim 4
Dependent Claim
15 words
The CMOS static RAM cell of claim 2 wherein the silicide layer is titanium silicide.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-04-07 | 1989-10-07 | 1990-04-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-04-07 | 1993-10-07 | 1994-04-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-04-07 | 1997-10-07 | 1998-04-08 | $7700.00 | Window Closed / Lapsed |