US4703552A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Fabricating a CMOS transistor having low threshold voltages using self-aligned silicide polysilicon gates and silicide interconnect regions
Assignee: STMicroelectronics SRL
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Filing: 1985-01-09
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Granted: 1987-11-03
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Expires: 2005-01-09
Abstract
Abstract The method provides for the formation of a layer of metal silicide on the gate layer of polycrystalline silicon and, for each transistor of the CMOS pair, the simultaneous doping of the active regions and the gate polycrystalline silicon. In the structure produced by this method, the gate electrodes are of polycrystalline silicon covered by metal silicide and the gate electrode of the n-channel transistor is doped with n-type material, while the gate electrode of the p-channel transistor is doped with p-type impurities. This enables the production of low threshold voltages for both transistors even in the case of very high integration densities.
Inventors
- 👤 Livio Baldi
- 👤 Giuseppe Corda
- 👤 Giulio Iannuzzi
- 👤 Danilo Re
- 👤 Giorgio De Santi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 21:09
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/60; H10D64/66; H10D64/661; H10D64/662; H10D64/663; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0172; H10D84/0174; H10D84/0177; H10D84/02; H10D84/03; H10D84/038; Y; Y10; Y10S; Y10S148/00; Y10S148/082
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
107 words
A method for forming N-channel and P-channel CMOS transistors having a low threshold voltage in a common silicon substrate, comprising the steps of: depositing a layer of polysilicon over said substrate; depositing a layer of metal silicide over said layer of polysilicon; forming mutually superimposed regions of said polysilicon layer and said metal silicide layer; implanting through superimposed regions of said metal silicide layer to provide a P-type polycrystalline silicon gate region and a P-type substrate region for said P-channel MOS transistor; and implanting through superimposed regions of said metal-silicide layer to provide an N-type gate region and a N-type substrate region for said N-channel MOS transistor.
Claim 2
Independent Claim
107 words
A method for forming N-channel and P-channel CMOS transistors having a low threshold voltage in a common silicon substrate, comprising the steps of: depositing a layer of polysilicon over said substrate; depositing a layer of metal silicide over said layer of polysilicon; forming mutually superimposed regions of said polysilicon layer and said metal silicide layer; implanting through superimposed regions of said metal silicide layer to provide a P-type polycrystalline silicon gate region and a P-type substrate region for said P-channel MOS transistor; and implanting through superimposed regions of said metal-silicide layer to provide an N-type gate region and a N-type substrate region for said N-channel MOS transistor.
Claim 3
Dependent Claim
18 words
The method according to claim 1, wherein said implanting steps also form self-aligned N-channel and P-channel MOS transistors.
Claim 4
Dependent Claim
18 words
The method according to claim 1, further including thermally oxidizing said superimposed portions of said metal silicide layer.
Claim 5
Dependent Claim
31 words
The method according to claim 1, further including forming a superimposed portion of said polysilicon layer directly on said substrate to couple said P-channel MOS transistor and said N-channel MOS transistor.
Claim 6
Independent Claim
93 words
A method for forming CMOS devices having low threshold voltages in a common substrate, comprising the steps of: forming a layer of polysilicon on said substrate; forming a layer of metal silicide on said layer of polysilicon; forming a pattern in said polysilicon layer and in said silicide layer so that said patterned polysilicon layer everywhere underlies said silicide layer; and implanting through said silicide layer to form complementary-doped gates for said CMOS devices and to form complementary source-drain regions in said substrate, said source-drain regions being contacted by said patterned polysilicon layer.
Claim 7
Independent Claim
93 words
A method for forming CMOS devices having low threshold voltages in a common substrate, comprising the steps of: forming a layer of polysilicon on said substrate; forming a layer of metal silicide on said layer of polysilicon; forming a pattern in said polysilicon layer and in said silicide layer so that said patterned polysilicon layer everywhere underlies said silicide layer; and implanting through said silicide layer to form complementary-doped gates for said CMOS devices and to form complementary source-drain regions in said substrate, said source-drain regions being contacted by said patterned polysilicon layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-11-02 | 1991-05-04 | 1991-11-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-11-02 | 1995-05-04 | 1995-11-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-11-02 | 1999-05-04 | 1999-11-03 | $7700.00 | Window Closed / Lapsed |