US5089429A
Expired / Lapsed
US
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Self-aligned emitter bicmos process
Assignee: Sarnoff Corp
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Filing: 1989-06-22
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Granted: 1992-02-18
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Expires: 2009-06-22
Abstract
Abstract A process is disclosed for forming bipolar transistors in a BiCMOS process which is fully compatible with the CMOS process used to form other devices in the same integrated circuit. The process produces bipolar transistor sizes which are compatible with the minimum size features and design rules of the CMOS process. A CVD silicon oxide layer to be used to form spacers is deposited on the top of emitter and gate electrodes covered with a first oxide layer.
Inventors
- 👤 Sheng T. Hsu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 20:52
CPC Classifications
H; H10; H10D; H10D10/00; H10D10/01; H10D10/051; H10D84/00; H10D84/01; H10D84/0107; H10D84/0109; H10D84/02; H10D84/03; H10D84/038
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
316 words
A method of forming a BiCMOS integrated circuit comprising the steps of: (a) forming a first semiconductor layer of one conductivity type on a substrate; (b) forming spaced well regions of the opposite conductivity type in said first semiconductor layer; (c) forming a thin oxide layer on the surface of the first semiconductor layer between the well regions and on one of said well regions; (d) simultaneously forming an emitter electrode on the surface of the first semiconductor layer in the other well region and gates on the thin oxide layer over the one well region and the surface of the first semiconductor layer between the well regions, said emitter electrode and each of said gates comprising a second semiconductor layer containing dopants of the second conductivity type and each having a first oxide layer over the top surface thereof; (e) diffusing the dopant from the emitter electrode into the other well region to form an emitter region; (f) depositing by chemical vapor deposition a second oxide layer over the first oxide layer, the side walls of the emitter electrode and gates and the surface of the first semiconductor layer immediately surrounding the emitter electrode and on opposite sides of the gates; (g) removing the second oxide layer from the first oxide layer and the surface of the first semiconductor layer immediately surrounding the emitter region and the opposite sides of the gates to leave side wall masking regions on the emitter electrode and the gates; (h) implanting dopants of the one conductivity type into each of the well regions immediately surrounding the emitter electrode to form a base region and on each side of the gate to form source and drain regions; and (i) implanting dopants of the opposite conductivity type into the surface of the first semiconductor between the well regions and at opposite sides of the gate to form source and drain regions.
Claim 2
Independent Claim
316 words
A method of forming a BiCMOS integrated circuit comprising the steps of: (a) forming a first semiconductor layer of one conductivity type on a substrate; (b) forming spaced well regions of the opposite conductivity type in said first semiconductor layer; (c) forming a thin oxide layer on the surface of the first semiconductor layer between the well regions and on one of said well regions; (d) simultaneously forming an emitter electrode on the surface of the first semiconductor layer in the other well region and gates on the thin oxide layer over the one well region and the surface of the first semiconductor layer between the well regions, said emitter electrode and each of said gates comprising a second semiconductor layer containing dopants of the second conductivity type and each having a first oxide layer over the top surface thereof; (e) diffusing the dopant from the emitter electrode into the other well region to form an emitter region; (f) depositing by chemical vapor deposition a second oxide layer over the first oxide layer, the side walls of the emitter electrode and gates and the surface of the first semiconductor layer immediately surrounding the emitter electrode and on opposite sides of the gates; (g) removing the second oxide layer from the first oxide layer and the surface of the first semiconductor layer immediately surrounding the emitter region and the opposite sides of the gates to leave side wall masking regions on the emitter electrode and the gates; (h) implanting dopants of the one conductivity type into each of the well regions immediately surrounding the emitter electrode to form a base region and on each side of the gate to form source and drain regions; and (i) implanting dopants of the opposite conductivity type into the surface of the first semiconductor between the well regions and at opposite sides of the gate to form source and drain regions.
Claim 3
Dependent Claim
46 words
The method claim 1 in which after the well regions are formed, the step of forming oxide isolation regions in the surface of the first semiconductor layer at the junctions of the well regions and the portion of the first semiconductor layer between the well regions.
Claim 4
Dependent Claim
50 words
The method of claim 2 including the steps of forming a high conductivity buried region of the opposite conductivity type between the substrate and the first semiconductor layer along the wells, and forming a high conductivity well of the opposite conductivity type through the other well to the buried region.
Claim 5
Dependent Claim
43 words
The method of claim 3 in which the wells are formed by implanting dopants of the opposite conductivity type into the surface of the first semiconductor layer and simultaneously diffusing the dopants of all the wells into and through the first semiconductor layer.
Claim 6
Dependent Claim
74 words
The method of claim 1 in which the emitter electrode, the gates and the first oxide layer on the top of each are formed by applying a layer of doped polysilicon over the surface of the first semiconductor layer and the thin oxide layer, forming a layer of an oxide over the polysilicon layer and then removing portions of the oxide layer and the polysilicon layer to form the emitter electrode and the gates.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-02-17 | 1995-08-19 | 1996-02-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-02-17 | 1999-08-19 | 2000-02-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-02-17 | 2003-08-19 | 2004-02-18 | $7700.00 | Window Closed / Lapsed |