Abstract A process for fabricating an electrically erasable nonvolatile memory cell comprises forming a first region of insulating material which is less than about 200 Angstroms thick on a selected surface portion of an electrically-isolated relatively lightly doped pocket of epitaxial silicon of a first conductivity type such that first and second surface areas of the epitaxial pocket are exposed. Regions of the epitaxial pocket underlying the first and second exposed surface areas are doped such that first and second relatively lightly doped regions of a second conductivity type are formed in the epitaxial pocket. Relatively heavily doped polysilicon regions of the first conductivity type are formed on the first insulating region and on the second relatively lightly doped epitaxial region. Insulating material is formed over exposed surfaces of the first polysilicon region and the second polysilicon region such that first and second surface portions of the second relatively lightly doped epitaxial region are exposed. The regions of the epitaxial pocket underlying the surface of the first relatively lightly doped epitaxial region and the first and second surface portions of the second relatively lightly doped epitaxial region are doped such that first, second and third relatively heavily doped epitaxial regions of the second conductivity type are formed in the epitaxial pocket. Relatively heavily doped polysilicon of the second conductivity type is formed on the insulating regions covering said first conductivity type polycrystalline regions.
A process for fabricating an oxide isolated electrically erasable memory cell semiconductor structure in an epitaxial layer of first conductivity type overlying a buried layer of first conductivity type, the process comprising the sequential steps of: (a) forming a first layer of insulating material of a thickness which permits tunneling of electrons therethrough over a first region of a substantially planar surface of the epitaxial layer; (b) introducing dopant of second conductivity type into all of the planar surface except the first region thereof; (c) forming a first region of polysilicon of first conductivity type on the first insulating layer and a second region of polysilicon of first conductivity type on a second region of the planar surface; (d) forming insulating material over all exposed surfaces of both the first and the second regions of polysilicon as well as over exposed areas of the planar surface; (e) patterning the insulating material to expose selected portions of the planar surface; (f) introducing dopant of second conductivity type into the exposed selected portions of the planar surface; (g) forming a first region of polysilicon of second conductivity type on the insulating material overlying the first region of polysilicon of first conductivity type and a second region of polysilicon of second conductivity type overlying the insulating material overlying the first region of polysilicon of first conductivity type; (h) forming insulating material over all exposed surfaces of both the first and the second regions of polysilicon of second conductivity type; and (i) forming a layer of conductive material over the structure formed according to steps a-h above such that the conductive material contacts the exposed selected portions of the planar surface.
Claim 2
Dependent Claim
277 words
A process for fabricating an oxide isolated electrically erasable memory cell semiconductor structure in an epitaxial layer of first conductivity type overlying a buried layer of first conductivity type, the process comprising the sequential steps of: (a) forming a first layer of insulating material of a thickness which permits tunneling of electrons therethrough over a first region of a substantially planar surface of the epitaxial layer; (b) introducing dopant of second conductivity type into all of the planar surface except the first region thereof; (c) forming a first region of polysilicon of first conductivity type on the first insulating layer and a second region of polysilicon of first conductivity type on a second region of the planar surface; (d) forming insulating material over all exposed surfaces of both the first and the second regions of polysilicon as well as over exposed areas of the planar surface; (e) patterning the insulating material to expose selected portions of the planar surface; (f) introducing dopant of second conductivity type into the exposed selected portions of the planar surface; (g) forming a first region of polysilicon of second conductivity type on the insulating material overlying the first region of polysilicon of first conductivity type and a second region of polysilicon of second conductivity type overlying the insulating material overlying the first region of polysilicon of first conductivity type; (h) forming insulating material over all exposed surfaces of both the first and the second regions of polysilicon of second conductivity type; and (i) forming a layer of conductive material over the structure formed according to steps a-h above such that the conductive material contacts the exposed selected portions of the planar surface.
Claim 3
Dependent Claim
21 words
A process as recited in claim 1 wherein the first layer of insulating material is less than about 200 Angstroms thick.
Claim 4
Dependent Claim
14 words
A process according to claim 1 wherein said first conductivity type is N type.
Claim 5
Dependent Claim
14 words
A process according to claim 1 wherein said second conductivity type is P type.
Claim 6
Dependent Claim
13 words
A process according to claim 1 wherein said insulating material is silicon dioxide.
Claim 7
Dependent Claim
13 words
A process according to claim 1 wherein said doping is by ion implantation.