US3893085A
Expired / Lapsed
US
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Read mostly memory cell having bipolar and FAMOS transistor
Assignee: International Business Machines Corp
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Filing: 1973-11-28
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Granted: 1975-07-01
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Expires: 1993-11-28
Abstract
Abstract Disclosed is a memory cell incorporating the major advantages of a read only storage (ROS) and having the flexibility of on-chip personalization after processing. In a memory matrix having orthogonally arranged bit lines and word lines with memory cells located at the cross points, each of the disclosed memory cells constructed in accordance with BIFET technology includes a floating gate avalanche breakdown MOS transistor (FAMOS) coupled to a bipolar transistor. The residual charge on the floating gate FAMOS transistor determines the logical state of the read mostly memory cell.
Inventors
- 👤 Aage A Hansen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 14:22
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0433; H; H10; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/684; H10D30/686; H10D84/00; H10D84/40; H10D84/401; H10D84/403; H10D84/406
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
31 words
A memory cell comprising: an input node; a transistor having collector, base, and emitter regions; and a FAMOS device connected between the base region of said transistor and said input node.
Claim 2
Dependent Claim
31 words
A memory cell comprising: an input node; a transistor having collector, base, and emitter regions; and a FAMOS device connected between the base region of said transistor and said input node.
Claim 3
Dependent Claim
35 words
A memory cell as in claim 1 wherein said FAMOS device connected between the base region of said transistor and said input node includes a substrate, a pair of gated electrodes, and a floating gate.
Claim 4
Dependent Claim
16 words
A memory cell as in claim 2 wherein said FAMOS device further comprises: an erase gate.
Claim 5
Dependent Claim
40 words
A memory cell as in claim 2 wherein the substrate of said FAMOS device is connected to the collector region of said transistor, the base of said transistor being integral with one of the gated electrodes of said FAMOS device.
Claim 6
Dependent Claim
68 words
A memory cell as in claim 4 wherein the other gated electrode of said FAMOS device is connected to said input node, said input node being a word line, the substrate of said FAMOS device being connected to a bit line, the emitter region of said transistor being left floating during a write operation, said emitter region being connected to a steady state potential during a read operation.
Claim 7
Dependent Claim
77 words
A memory array comprising: a plurality of bit lines arranged in a substantially parallel relationship with respect to each other; a plurality of word lines arranged in a substantially parallel relationship with each other and forming a matrix in a substantially perpendicular relationship with said bit lines; and a plurality of memory cells as in claim 5, each of said cells having an electrical connection to one of said word lines and one of said bit lines.
Claim 8
Dependent Claim
77 words
A memory array comprising: a plurality of bit lines arranged in a substantially paraLlel relationship with respect to each other; a plurality of word lines arranged in a substantially parallel relationship with each other and forming a matrix in a substantially perpendicular relationship with said bit lines; and a plurality of memory cells as in claim 4, each of said cells having an electrical connection to one of said word lines and one of said bit lines.
Claim 9
Dependent Claim
77 words
A memory array comprising: a plurality of bit lines arranged in a substantially parallel relationship with respect to each other; a plurality of word lines arranged in a substantially parallel relationship with each other and forming a matrix in a substantially perpendicular relationship with said bit lines; and a plurality of memory cells as in claim 2, each of said cells having an electrical connection to one of said word lines and one of said bit lines.
Claim 10
Dependent Claim
77 words
A memory array comprising: a plurality of bit lines arranged in a substantially parallel relationship with respect to each other; a plurality of word lines arranged in a substantially parallel relationship with each other and forming a matrix in a substantially perpendicular relationship with said bit lines; and a plurality of memory cells as in claim 1, each of said cells having an electrical connection to one of said word lines and one of said bit lines.
Claim 11
Dependent Claim
57 words
A memory cell as in claim 1 having a monolithically integrated structure comprising: a first common semiconductor region forming one of the gated regions of said FAMOS device and the base region of said transistor; and a second common region forming the substrate of said FAMOS device and a contact for the subcollector region of said transistor.
Claim 12
Dependent Claim
101 words
A monolithically integrated memory cell structure comprising: a substrate being doped with an impurity of a first conductivity type; a subcollector region formed in said substrate, said subcollector region being doped with an impurity of a second conductivity type; an epitaxial layer formed over said substrate, said epitaxial layer being doped with an impurity of said second conductivity type; at least two pockets of said first conductivity type formed in said epitaxial layer; a region of said second conductivity type formed in one of said pockets; and a floating gate formed over a portion of said epitaxial layer between said pockets.
Claim 13
Dependent Claim
101 words
A monolithically integrated memory cell structure comprising: a substrate being doped with an impurity of a first conductivity type; a subcollector region formed in said substrate, said subcollector region being doped with an impurity of a second conductivity type; an epitaxial layer formed over said substrate, said epitaxial layer being doped with an impurity of said second conductivity type; at least two pockets of said first conductivity type formed in said epitaxial layer; a region of said second conductivity type formed in one of said pockets; and a floating gate formed over a portion of said epitaxial layer between said pockets.
Claim 14
Dependent Claim
16 words
A memory cell structure as in claim 11 wherein said subcollector region forms a bit/sense line.
Claim 15
Dependent Claim
35 words
A monolithic memory cell structure as in claim 11 wherein said at least two pockets form the gated electrodes of a FAMOS device, one of said pockets also forming the base region of a transistor.
Claim 16
Dependent Claim
34 words
A monolithically integrated memory cell structure as in claim 11 wherein a portion of said epitaxial layer forms the substrate of a FAMOS device and a contact for the subcollector region of a transistor.
Claim 17
Dependent Claim
29 words
A monolithically integrated memory cell structure as in claim 11 wherein said region of second conductivity type formed in one of said pockets forms the emitter of a transistor.
Claim 18
Dependent Claim
24 words
A monolithically integrated memory structure as in claim 11 further comprising: an erase gate formed over at least a portion of said floating gate.
Claim 19
Dependent Claim
48 words
A memory cell comprising: an input node; a transistor having collector, base, and emitter regions; and a field effect device having drain source and gate regions and adapted to receive trapped charge in the gate region, connected between the base region of said transistor and said input node.
Claim 20
Dependent Claim
48 words
A memory cell comprising: an input node; a transistor having collector, base, and emitter regions; and a field effect device having drain source and gate regions and adapted to receive trapped charge in the gate region, connected between the base region of said transistor and said input node.
Claim 21
Dependent Claim
52 words
A memory cell comprising: an input node; a transistor having collector, base, and emitter regions; and a field effect device having drain source and gate regions connected between the base region of said transistor and said input node, said field effect device having a substrate region electrically common with said collector region.
Claim 22
Dependent Claim
52 words
A memory cell comprising: an input node; a transistor having collector, base, and emitter regions; and a field effect device having drain source and gate regions connected between the base region of said transistor and said input node, said field effect device having a substrate region electrically common with said collector region.
Claim 23
Dependent Claim
103 words
Monolithically integrated memory cell structure comprising: a first region being doped with aN impurity of a first conductivity type; a second region formed in said first region, said second region being doped with an impurity of a second conductivity type; a third region formed over said first region, said third region being doped with an impurity of said second conductivity type; at least two pockets of said first conductivity type formed in said third region; a fourth region of said second conductivity type formed in one of said pockets; and a gate formed over a portion of said third region between said pockets.
Claim 24
Dependent Claim
103 words
Monolithically integrated memory cell structure comprising: a first region being doped with aN impurity of a first conductivity type; a second region formed in said first region, said second region being doped with an impurity of a second conductivity type; a third region formed over said first region, said third region being doped with an impurity of said second conductivity type; at least two pockets of said first conductivity type formed in said third region; a fourth region of said second conductivity type formed in one of said pockets; and a gate formed over a portion of said third region between said pockets.
References Cited (Backward Citations)
US3660819A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-06-30 | 1978-12-30 | 1979-07-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-06-30 | 1982-12-30 | 1983-07-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-06-30 | 1986-12-30 | 1987-07-01 | $7700.00 | Window Closed / Lapsed |