Semiconductor memory device and method of manufacturing the same

Claim 2

A semiconductor memory device provided with static memory cells comprising: a semiconductor substrate having a main surface and provided at said main surface with a groove; and an access transistor having a pair of source/drain regions formed at said main surface and spaced from each other, wherein one of said source/drain regions of said access transistor has: a first impurity region formed at said main surface and having a first diffusion depth from said main surface, a second impurity region formed at said main surface, being in contact with an end of said first impurity region on the side of the other of said source/drain regions, and having a smaller impurity concentration than said first impurity region, and a third impurity region spaced from said second impurity region with said first impurity region therebetween, formed at a whole bottom surface of said groove, and having a second diffusion depth from the bottom surface of said groove smaller than said first diffusion depth.

Claim 3

The semiconductor memory device according to claim 1, wherein said third impurity region has a lower impurity concentration than said first impurity region.

Claim 4

The semiconductor memory device according to claim 1 further comprising: a driver transistor having a pair of source/drain regions formed at said main surface and spaced from each other, and a gate electrode layer formed on a region between said pair of source/drain regions with a gate insulating layer therebetween, wherein an impurity concentration of said semiconductor substrate immediately under said groove is lower, at a depth of a junction between said semiconductor substrate and said third impurity region arranged at the bottom of said groove, than the impurity concentration of said semiconductor substrate immediately under said gate electrode layer of said driver transistor.

Claim 5

The semiconductor memory device according to claim 1, wherein a depth from said main surface to the bottom surface of said groove is 300 Å or more.

Claim 6

The semiconductor memory device according to claim 1, further comprising: a driver transistor having a pair of source/drain regions formed at said main surface and spaced from each other, and a gate electrode layer formed on a region between said pair of source/drain regions with a gate insulating layer therebetween; and a load element having one end electrically connected to said gate electrode layer of said driver transistor, and another end connected to a power supply potential line.

Claim 7

The semiconductor memory device according to claim 5, wherein said gate electrode layer of said driver transistor is in contact with a surface of one of said source/drain regions of said access transistor, and said one end of said load element is in contact with the surface of said gate electrode layer of said driver transistor.

Claim 8

The semiconductor memory device according to claim 5, wherein said one end of said load element is in contact with a surface of said gate electrode layer of said driver transistor and a surface of one of said source/drain regions of said access transistor.

Claim 9

The semiconductor memory device according to claim 5, wherein said gate electrode layer of said driver transistor is in contact with a surface of one of said source/drain regions of said access transistor, and said one end of said load element is in contact with the surface of said gate electrode layer of said driver transistor and the surface of one of said source/drain regions of said access transistor.

Claim 10

The semiconductor memory device according to claim 5, wherein said load element is a resistance.

Claim 11

The semiconductor memory device according to claim 5, wherein said load element is a thin-film transistor, and the end of said load element electrically connected to said gate electrode layer of said driver transistor is either a drain region or a gate electrode layer of said thin-film transistor.

Claim 12

A semiconductor memory device provided with static memory cells comprising: a semiconductor substrate having a main surface and provided at said main surface with a groove; a driver transistor having a pair of source/drain regions formed at said main surface and spaced from each other; said source region of said driver transistor having a first impurity region formed at said main surface and having a first diffusion depth from said main surface, and a second impurity region formed at said main surface, being in contact with an end of said first impurity region on said drain region side, and having a lower impurity concentration than said first impurity region; and an access transistor having a pair of source/drain regions formed at said main surface and spaced from each other, wherein one of said source/drain regions of said access transistor is formed at a whole bottom surface of said groove, and has a second diffusion depth from the bottom surface of said groove smaller than said first diffusion depth.

Claim 13

A semiconductor memory device provided with static memory cells comprising: a semiconductor substrate having a main surface and provided at said main surface with a groove; a driver transistor having a pair of source/drain regions formed at said main surface and spaced from each other; said source region of said driver transistor having a first impurity region formed at said main surface and having a first diffusion depth from said main surface, and a second impurity region formed at said main surface, being in contact with an end of said first impurity region on said drain region side, and having a lower impurity concentration than said first impurity region; and an access transistor having a pair of source/drain regions formed at said main surface and spaced from each other, wherein one of said source/drain regions of said access transistor is formed at a whole bottom surface of said groove, and has a second diffusion depth from the bottom surface of said groove smaller than said first diffusion depth.

Claim 14

The semiconductor memory device according to claim 11, wherein one of said source/drain regions of said access transistor has a lower impurity concentration than said first impurity region.

Claim 15

The semiconductor memory device according to claim 11, wherein said drain region of said driver transistor and said pair of source/drain regions of said access transistor have impurity concentrations of 1×10 19 cm -3 or less.

Claim 16

A semiconductor memory device provided with static memory cells and a peripheral circuit comprising: a semiconductor substrate having a main surface and provided at said main surface with a groove; an MIS transistor included in said peripheral circuit and having a pair of source/drain regions formed at said main surface and spaced from each other; one of said source/drain regions of said MIS transistor having: a first impurity region formed at said main surface and having a first diffusion depth from said main surface, a second impurity region formed at said main surface, being in contact with an end of said first impurity region on the side of the other of said source/drain regions, and having a lower impurity concentration than said first impurity region; and an access transistor having a pair of source/drain regions formed at said main surface and spaced from each other, wherein one of said source/drain regions of said access transistor is formed at a whole bottom surface of said groove, and has a second diffusion depth from the bottom surface of said groove smaller than said first diffusion depth.

Claim 17

A semiconductor memory device provided with static memory cells and a peripheral circuit comprising: a semiconductor substrate having a main surface and provided at said main surface with a groove; an MIS transistor included in said peripheral circuit and having a pair of source/drain regions formed at said main surface and spaced from each other; one of said source/drain regions of said MIS transistor having: a first impurity region formed at said main surface and having a first diffusion depth from said main surface, a second impurity region formed at said main surface, being in contact with an end of said first impurity region on the side of the other of said source/drain regions, and having a lower impurity concentration than said first impurity region; and an access transistor having a pair of source/drain regions formed at said main surface and spaced from each other, wherein one of said source/drain regions of said access transistor is formed at a whole bottom surface of said groove, and has a second diffusion depth from the bottom surface of said groove smaller than said first diffusion depth.

Claim 18

The semiconductor memory device according to claim 14, wherein one of said source/drain regions of said access transistor has a lower impurity concentration than said first impurity region.

Claim 19

The semiconductor memory device according to claim 14, further comprising a driver transistor having a pair of source/drain regions formed at said main surface and spaced from each other, and a gate electrode layer formed on a region between said pair of source/drain regions with a gate insulating layer therebetween, wherein said pair of source/drain regions of said driver transistor and said pair of source/drain regions of said access transistor have impurity concentrations of 1×10 19 cm -3 or less.

Claim 20

The semiconductor memory device according to claim 14, further comprising: a driver transistor having a pair of source/drain regions formed at said main surface and spaced from each other, and a gate electrode layer formed on a region between said pair of source/drain regions with a gate insulating layer therebetween, wherein a silicide layer is formed in contact with the surface of said source region of said driver transistor.

Claim 21

The semiconductor memory device according to claim 14, wherein said pair of source/drain regions of said access transistor contain arsenic as impurity introduced thereinto, and said pair of source/drain regions of said MIS transistor included in said peripheral circuit contain phosphorus as impurity introduced thereinto.

Claim 22

A semiconductor memory device provided with static memory cells and a peripheral circuit comprising: a semiconductor substrate having a main surface; an MIS transistor having a source/drain region formed at said main surface, and included in said peripheral circuit; said source/drain region of said MIS transistor having a first impurity region formed at said main surface under a side wall insulating layer formed on a side wall of a gate electrode of said MIS transistor, and a conductive layer being in contact with said first impurity region and having a lower resistance than that of said first impurity region; an access transistor having a source/drain region formed at said main surface and including a second impurity region having higher resistance than that of said conductive layer; and driver transistor having a source/drain region formed at said main surface and including a third impurity region having higher resistance than that of said conductive layer and a silicide layer formed on said third impurity region only on a source region side.

Claim 23

A semiconductor memory device provided with static memory cells and a peripheral circuit comprising: a semiconductor substrate having a main surface; an MIS transistor having a source/drain region formed at said main surface, and included in said peripheral circuit; said source/drain region of said MIS transistor having a first impurity region formed at said main surface under a side wall insulating layer formed on a side wall of a gate electrode of said MIS transistor, and a conductive layer being in contact with said first impurity region and having a lower resistance than that of said first impurity region; an access transistor having a source/drain region formed at said main surface and including a second impurity region having higher resistance than that of said conductive layer; and driver transistor having a source/drain region formed at said main surface and including a third impurity region having higher resistance than that of said conductive layer and a silicide layer formed on said third impurity region only on a source region side.

Claim 24

The semiconductor memory device according to claim 19, characterized in that said conductive layer is formed of an impurity region having a higher concentration than that of said first impurity region.

Claim 25

The semiconductor memory device according to claim 19, characterized in that said conductive layer is formed of a silicide layer formed on said first impurity region.

Claim 26

The semiconductor memory device according to claim 19, characterized in that said first impurity region is formed of phosphorous, and said second impurity region and said third impurity region are formed of arsenic.