Semiconductor device having a source-drain region of a load transistor that is formed by implanting an impurity using an insulation layer as a mask

Claim 2

A semiconductor device, comprising: a first conductivity type of driver transistor; a second conductivity type of load transistor formed on the driver transistor; and an insulation layer formed between the driver transistor and the load transistor; wherein the insulation layer is provided thereon with a depression area in which a channel region, a gate insulation layer and a gate electrode of the load transistor are formed; and wherein the load transistor is a bottom-gate type, in which the gate electrode of the load transistor is provided under the channel region.

Claim 3

The semiconductor device according to claim 1, wherein: said depression area is a groove.

Claim 4

The semiconductor device according to claim 2, wherein: said groove is formed to be forward tapered shape, the bottom being narrower than the upper opening.

Claim 5

The semiconductor device according to claim 1, wherein: said first and second conductivity types are N-type and P-type, respectively.

Claim 6

The semiconductor device according to claim 1, wherein: said channel region and a source-drain region of the load transistor are formed in a self-alignment fashion by implanting impurity.

Claim 7

The semiconductor device according to claim 5, wherein: said impurity is boron.

Claim 8

A semiconductor memory, comprising: a pair of N-type driver transistors; a pair of P-type load transistors formed on the driver transistors; and an insulation layer formed between the driver transistors and the load transistors; wherein the insulation layer is provided thereon with a groove in which channel regions, gate insulation layers and gate electrodes of the load transistors are formed, and wherein the load transistors are each a bottom-gate type, in which the gate electrodes of the load transistors are provided under said channel regions.

Claim 9

A semiconductor memory, comprising: a pair of N-type driver transistors; a pair of P-type load transistors formed on the driver transistors; and an insulation layer formed between the driver transistors and the load transistors; wherein the insulation layer is provided thereon with a groove in which channel regions, gate insulation layers and gate electrodes of the load transistors are formed, and wherein the load transistors are each a bottom-gate type, in which the gate electrodes of the load transistors are provided under said channel regions.

Claim 10

The semiconductor memory according to claim 7, wherein: said channel regions and source-drain regions of the load transistors are formed in a self-alignment fashion by implanting impurity.

Claim 11

A semiconductor device comprising: a first conductivity type of driver transistor; a second conductivity type of load transistor; a first insulation layer formed between said driver transistor and said load transistor; a grooved formed on said first insulation layer; a first contact hole for contacting a gate electrode of said driver transistor and a gate electrode of said load transistor; a gate insulation layer formed on said gate electrode of said load transistor; a second contact hole formed on said gate insulation layer; a substrate region of said load transistor formed on said gate insulation layer; a channel region of said load transistor formed in said groove; and an insulation layer formed on said substrate region of said load transistor, said insulation layer having a sufficient thickness for filling said channel region of said load transistor formed in said groove; wherein said insulation layer is located only on said channel region of said load transistor; and wherein a source-drain region of said load transistor is formed in a self-alignment fashion by implanting an impurity and by using said insulation layer as a mask.

Claim 12

A semiconductor device comprising: a first conductivity type of driver transistor; a second conductivity type of load transistor; a first insulation layer formed between said driver transistor and said load transistor; a grooved formed on said first insulation layer; a first contact hole for contacting a gate electrode of said driver transistor and a gate electrode of said load transistor; a gate insulation layer formed on said gate electrode of said load transistor; a second contact hole formed on said gate insulation layer; a substrate region of said load transistor formed on said gate insulation layer; a channel region of said load transistor formed in said groove; and an insulation layer formed on said substrate region of said load transistor, said insulation layer having a sufficient thickness for filling said channel region of said load transistor formed in said groove; wherein said insulation layer is located only on said channel region of said load transistor; and wherein a source-drain region of said load transistor is formed in a self-alignment fashion by implanting an impurity and by using said insulation layer as a mask.

Claim 13

A semiconductor device, according to claim 9, wherein said gate electrode of said load transistor is provided under said substrate region of said load transistor and said gate insulation layer, and wherein said gate electrode and said channel region of said load transistor are formed in said groove provided in said insulation layer formed on said driver transistor.

Claim 14

A semiconductor device, according to claim 9, wherein said load transistor is a thin film PMOS load transistor.

Claim 15

A semiconductor device, according to claim 9, wherein said first and second conductivity types are N-type and P-type, respectively.

Claim 16

A semiconductor device, according to claim 12, wherein said impurity is boron.

Claim 17

A semiconductor device comprising: a pair of N-type of driver transistors; a pair of P-type of load transistors formed on the driver transistors; a first insulation layer formed between said driver transistors and said load transistors; a grooved formed on said first insulation layer; a first contact hole for contacting respective gate electrodes of said driver transistors and respective gate electrodes of said load transistors; a gate insulation layer formed on said gate electrodes of said load transistors; a second contact hole formed on said gate insulation layer; a substrate region of said load transistors formed on said gate insulation layer; a channel region of said load transistors formed in said groove; and an insulation layer formed on said substrate region of said load transistors, said insulation layer having a sufficient thickness for filling said channel region of said load transistors formed in said groove; wherein said insulation layer is located only on said channel region of said load transistor; and wherein respective source-drain regions of said load transistors are formed in a self-alignment fashion by implanting an impurity and by using said insulation layer as a mask.

Claim 18

A semiconductor device comprising: a pair of N-type of driver transistors; a pair of P-type of load transistors formed on the driver transistors; a first insulation layer formed between said driver transistors and said load transistors; a grooved formed on said first insulation layer; a first contact hole for contacting respective gate electrodes of said driver transistors and respective gate electrodes of said load transistors; a gate insulation layer formed on said gate electrodes of said load transistors; a second contact hole formed on said gate insulation layer; a substrate region of said load transistors formed on said gate insulation layer; a channel region of said load transistors formed in said groove; and an insulation layer formed on said substrate region of said load transistors, said insulation layer having a sufficient thickness for filling said channel region of said load transistors formed in said groove; wherein said insulation layer is located only on said channel region of said load transistor; and wherein respective source-drain regions of said load transistors are formed in a self-alignment fashion by implanting an impurity and by using said insulation layer as a mask.

Claim 19

A semiconductor device, according to claim 14, wherein said impurity is boron.